feat(allwinner): add function to detect H616 die variant

Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, that
differs in the way the CPU cores' power and reset controls are handled.
This die variation can be detected by reading the SRAM version register.

Provide a predicate function that returns false if that die variant is
used. Since the CPU power control code is shared for all supported SoCs,
we provide an instance of this function for each SoC, as a static
inline, and return true on all other SoCs. This allows to always use
this function, and still let the compiler optimise away the unneeded
branch for those older SoCs.

This function is unused for now, but is needed in the next patch.

Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-04-03 21:33:45 +01:00
parent b15e2cda14
commit fbde260b11
6 changed files with 24 additions and 1 deletions

View file

@ -28,4 +28,9 @@
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0 #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 4 #define SUNXI_AA64nAA32_OFFSET 4
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}
#endif /* SUNXI_CPUCFG_H */ #endif /* SUNXI_CPUCFG_H */

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@ -20,6 +20,7 @@
#define SUNXI_SOC_H616 0x1823 #define SUNXI_SOC_H616 0x1823
#define SUNXI_SOC_R329 0x1851 #define SUNXI_SOC_R329 0x1851
#define SUNXI_VER_BITS_MASK 0xffU
#define JEDEC_ALLWINNER_BKID 9U #define JEDEC_ALLWINNER_BKID 9U
#define JEDEC_ALLWINNER_MFID 0x9eU #define JEDEC_ALLWINNER_MFID 0x9eU

View file

@ -183,5 +183,5 @@ int32_t plat_get_soc_revision(void)
{ {
uint32_t reg = mmio_read_32(SRAM_VER_REG); uint32_t reg = mmio_read_32(SRAM_VER_REG);
return reg & GENMASK_32(7, 0); return reg & SUNXI_VER_BITS_MASK;
} }

View file

@ -36,4 +36,9 @@
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24 #define SUNXI_AA64nAA32_OFFSET 24
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}
#endif /* SUNXI_CPUCFG_H */ #endif /* SUNXI_CPUCFG_H */

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@ -1 +1,6 @@
#include <sunxi_cpucfg_ncat.h> #include <sunxi_cpucfg_ncat.h>
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}

View file

@ -1 +1,8 @@
#include <plat/common/platform.h>
#include <sunxi_cpucfg_ncat.h> #include <sunxi_cpucfg_ncat.h>
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return (plat_get_soc_revision() != 2);
}