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Merge "feat(intel): pinmux and power manager config for Agilex5 platform" into integration

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This commit is contained in:
Mark Dykes 2024-10-24 16:51:43 +02:00 • committed by TrustedFirmware Code Review
commit fa41430987
3 changed files with 63 additions and 37 deletions
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21
plat/intel/soc/agilex5/include/agilex5_pinmux.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,19 +8,13 @@
#ifndef AGX5_PINMUX_H
#define AGX5_PINMUX_H
/* PINMUX REGISTER ADDRESS */
#define AGX5_PINMUX_PIN0SEL 0x10d13000
#define AGX5_PINMUX_IO0CTRL 0x10d13130
#define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300
#define AGX5_PINMUX_IO0_DELAY 0x10d13400
#define AGX5_PERIPHERAL 0x10d14044
#include "socfpga_handoff.h"
/* PINMUX DEFINE */
#define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec
#define PINMUX_HANDOFF_CONFIG_VAL 0x7e000
/* PINMUX REGISTER ADDRESS */
#define AGX5_PINMUX_PIN0SEL 0x10D13000
#define AGX5_PINMUX_IO0CTRL 0x10D13130
#define AGX5_PINMUX_EMAC0_USEFPGA 0x10D13300
#define AGX5_PINMUX_IO0_DELAY 0x10D13400
/* Macros */
#define SOCFPGA_PINMUX_SEL_NAND (0x03)
@ -142,6 +137,9 @@
#define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50)
#define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54)
#define SOCFPGA_PINUMX_USEFPGA(_reg) (AGX5_PINMUX_EMAC0_USEFPGA \
+ SOCFPGA_PINMUX_##_reg)
#define SOCFPGA_PINMUX_IO0DELAY (0x00)
#define SOCFPGA_PINMUX_IO1DELAY (0x04)
#define SOCFPGA_PINMUX_IO2DELAY (0x08)
@ -198,5 +196,4 @@
+ (SOCFPGA_PINMUX_##_reg))
void config_pinmux(handoff *handoff);
void config_peripheral(handoff *handoff);
#endif

72
plat/intel/soc/agilex5/soc/agilex5_pinmux.c
View file

@ -187,14 +187,54 @@ const uint32_t sysmgr_pinmux_array_iodelay[] = {
0x0000011c, 0x00000000
};
void config_fpgaintf_mod(void)
static void config_fpgaintf_mod(void)
{
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
uint32_t fpgaintf_en_val;
/*
* System manager FPGA interface enable2 register, disable individual
* interfaces between the FPGA and HPS.
*/
fpgaintf_en_val = 0U;
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(NAND_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(4);
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SDMMC_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(8);
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM0_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(16);
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM1_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(24);
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), fpgaintf_en_val);
/*
* System manager FPGA interface enable3 register, disable individual
* interfaces between the FPGA and HPS.
*/
fpgaintf_en_val = 0U;
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC0_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(0);
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC1_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(8);
if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC2_USEFPGA)) & 0x01) != 0)
fpgaintf_en_val |= BIT(16);
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), fpgaintf_en_val);
}
void config_pinmux(handoff *hoff_ptr)
{
unsigned int i;
uint32_t i;
/* Configure the pin selection */
for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
mmio_write_32(AGX5_PINMUX_PIN0SEL + hoff_ptr->pinmux_sel_array[i],
hoff_ptr->pinmux_sel_array[i+1]);
}
/* Configure the pin control */
for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_io_array); i += 2) {
mmio_write_32(AGX5_PINMUX_IO0CTRL + hoff_ptr->pinmux_io_array[i],
hoff_ptr->pinmux_io_array[i+1]);
}
/*
* Configure the FPGA use.
@ -207,24 +247,12 @@ void config_pinmux(handoff *hoff_ptr)
hoff_ptr->pinmux_fpga_array[i+1]);
}
/* Configure the IO delay */
for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_iodelay_array); i += 2) {
mmio_write_32(AGX5_PINMUX_IO0_DELAY + hoff_ptr->pinmux_iodelay_array[i],
hoff_ptr->pinmux_iodelay_array[i+1]);
}
/* Enable/Disable individual interfaces between the FPGA and HPS */
config_fpgaintf_mod();
}
void config_peripheral(handoff *hoff_ptr)
{
// TODO: This need to be update due to peripheral_pwr_gate_array handoff change
// Pending SDM to pass over handoff data
// unsigned int i;
// for (i = 0; i < 4; i += 2) {
// mmio_write_32(AGX_EDGE_PERIPHERAL +
// hoff_ptr->peripheral_pwr_gate_array[i],
// hoff_ptr->peripheral_pwr_gate_array[i+1]);
// }
// TODO: This need to be update due to peripheral_pwr_gate_array handoff change
mmio_write_32(AGX5_PERIPHERAL,
hoff_ptr->peripheral_pwr_gate_array);
}

7
plat/intel/soc/agilex5/soc/agilex5_power_manager.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,7 +14,7 @@
#include "agilex5_power_manager.h"
#include "socfpga_reset_manager.h"
int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff)
static int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff)
{
uint32_t data = 0;
uint32_t count = 0;
@ -38,7 +39,7 @@ int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff)
return 0;
}
int pss_sram_power_off(handoff *hoff_ptr)
static int pss_sram_power_off(handoff *hoff_ptr)
{
int ret = 0;
uint32_t peripheral_handoff = 0;
@ -66,7 +67,7 @@ void config_pwrmgr_handoff(handoff *hoff_ptr)
{
int ret = 0;
switch (hoff_ptr->header_magic) {
switch (hoff_ptr->peripheral_pwr_gate_magic) {
case HANDOFF_MAGIC_PERIPHERAL:
ret = pss_sram_power_off(hoff_ptr);
break;