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aarch32: Fix L2CTRL definition for Cortex A57 and A72

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Fixes ARM-software/tf-issues#495

Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This commit is contained in:
Dimitris Papastamos 2017-06-13 12:33:39 +01:00
parent 94f7d1e205
commit f9688f2755
2 changed files with 2 additions and 2 deletions
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2
include/lib/cpus/aarch32/cortex_a57.h
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@ -55,7 +55,7 @@
/******************************************************************************* /*******************************************************************************
* L2 Control register specific definitions. * L2 Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3 #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6

2
include/lib/cpus/aarch32/cortex_a72.h
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@ -37,7 +37,7 @@
/******************************************************************************* /*******************************************************************************
* L2 Control register specific definitions. * L2 Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3 #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6