fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.

Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

drivers/nxp/clk/s32cc/s32cc_clk_drv.c

@@ -553,6 +553,7 @@ static int enable_mux(const struct s32cc_clk_obj *module,
 	switch (mux->module) {
 	/* PLL mux will be enabled by PLL setup */
 	case S32CC_ARM_PLL:
+	case S32CC_PERIPH_PLL:
 		break;
 	case S32CC_CGM1:
 		ret = enable_cgm_mux(mux, drv);