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drivers: allwinner: axp: Add AXP805 support
This adds the new regulator list, as well as changes to make the switch (equivalent to DC1SW on the AXP803) work on both PMICs. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311
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3 changed files with 52 additions and 12 deletions
33
drivers/allwinner/axp/axp805.c
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33
drivers/allwinner/axp/axp805.c
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@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/allwinner/axp.h>
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const uint8_t axp_chip_id = AXP805_CHIP_ID;
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const char *const axp_compatible = "x-powers,axp805";
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/*
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* The "dcdcd" split changes the step size by a factor of 5, not 2;
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* disallow values above the split to maintain accuracy.
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*/
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const struct axp_regulator axp_regulators[] = {
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{"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0},
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{"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1},
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{"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2},
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{"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3},
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{"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4},
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{"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5},
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{"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6},
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{"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7},
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{"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0},
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{"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1},
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{"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2},
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{"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3},
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{"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4},
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{"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5},
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{"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6},
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{}
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};
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@ -108,7 +108,7 @@ static bool should_enable_regulator(const void *fdt, int node)
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void axp_setup_regulators(const void *fdt)
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void axp_setup_regulators(const void *fdt)
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{
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{
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int node;
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int node;
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bool dc1sw = false;
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bool sw = false;
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if (fdt == NULL)
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if (fdt == NULL)
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return;
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return;
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@ -120,6 +120,7 @@ void axp_setup_regulators(const void *fdt)
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return;
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return;
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}
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}
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/* This applies to AXP803 only. */
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if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
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if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
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axp_clrbits(0x8f, BIT(4));
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axp_clrbits(0x8f, BIT(4));
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axp_setbits(0x30, BIT(2));
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axp_setbits(0x30, BIT(2));
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@ -144,26 +145,31 @@ void axp_setup_regulators(const void *fdt)
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continue;
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continue;
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name = fdt_get_name(fdt, node, &length);
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name = fdt_get_name(fdt, node, &length);
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/* Enable the switch last to avoid overheating. */
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if (!strncmp(name, "dc1sw", length) ||
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!strncmp(name, "sw", length)) {
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sw = true;
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continue;
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}
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for (reg = axp_regulators; reg->dt_name; reg++) {
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for (reg = axp_regulators; reg->dt_name; reg++) {
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if (!strncmp(name, reg->dt_name, length)) {
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if (!strncmp(name, reg->dt_name, length)) {
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setup_regulator(fdt, node, reg);
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setup_regulator(fdt, node, reg);
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break;
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break;
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}
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}
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}
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}
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if (!strncmp(name, "dc1sw", length)) {
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/* Delay DC1SW enablement to avoid overheating. */
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dc1sw = true;
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continue;
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}
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}
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}
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/*
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/*
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* If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts
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* On the AXP803, if DLDO2 is enabled after DC1SW, the PMIC overheats
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* down. So always enable DC1SW as the very last regulator.
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* and shuts down. So always enable DC1SW as the very last regulator.
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*/
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*/
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if (dc1sw) {
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if (sw) {
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INFO("PMIC: Enabling DC1SW\n");
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INFO("PMIC: Enabling DC SW\n");
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axp_setbits(0x12, BIT(7));
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if (axp_chip_id == AXP803_CHIP_ID)
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axp_setbits(0x12, BIT(7));
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if (axp_chip_id == AXP805_CHIP_ID)
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axp_setbits(0x11, BIT(7));
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}
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}
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}
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}
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@ -13,6 +13,7 @@
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enum {
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enum {
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AXP803_CHIP_ID = 0x41,
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AXP803_CHIP_ID = 0x41,
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AXP805_CHIP_ID = 0x40,
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};
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};
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struct axp_regulator {
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struct axp_regulator {
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