diff --git a/changelog.yaml b/changelog.yaml index d073a8427..5224441cc 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -272,6 +272,13 @@ subsections: - title: Corstone-1000 scope: corstone-1000 + - title: Automotive RD + scope: automotive_rd + + subsections: + - title: RD-1 AE + scope: rd1ae + - title: Aspeed scope: aspeed diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 8bb12abbd..4d08a7f58 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -594,6 +594,16 @@ Arm Total Compute platform port :|G|: `rupsin01`_ :|F|: plat/arm/board/tc +Arm Automotive RD platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Diego Sueiro +:|G|: `diego-sueiro`_ +:|M|: Peter Hoyes +:|G|: `hoyes`_ +:|M|: Divin Raj +:|G|: `divin-raj`_ +:|F|: plat/arm/board/automotive_rd + Aspeed platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Chia-Wei Wang @@ -1041,12 +1051,15 @@ Conventional Changelog Extensions .. _CJKay: https://github.com/cjkay .. _danh-arm: https://github.com/danh-arm .. _davidvincze: https://github.com/davidvincze +.. _diego-sueiro: https://github.com/diego-sueiro +.. _divin-raj: https://github.com/divin-raj .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo .. _gprocopciucnxp: https://github.com/gprocopciucnxp .. _grandpaul: https://github.com/grandpaul .. _harrisonmutai-arm: https://github.com/harrisonmutai-arm .. _hilamirandakuzi1: https://github.com/hilamirandakuzi1 +.. _hoyes: https://github.com/hoyes .. _hzhuang1: https://github.com/hzhuang1 .. _hugues-kambampiana-arm: https://github.com/hugueskamba .. _JackyBai: https://github.com/JackyBai diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S new file mode 100644 index 000000000..8efe8acb1 --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include + +/* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * + * There are currently no platform specific regs + * to print. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h new file mode 100644 index 000000000..3bb719a12 --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include + +/* These are referenced by arm_def.h #included next, so #define first. */ +#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0) + +#include +#include +#include + +#define PLATFORM_CORE_COUNT U(16) +#define PLAT_ARM_CLUSTER_COUNT U(16) +#define PLAT_MAX_CPUS_PER_CLUSTER U(1) +#define PLAT_MAX_PE_PER_CPU U(1) + +#define PLATFORM_STACK_SIZE UL(0x1000) + +/* BL1 is not supported */ +#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0) +#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0) + +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) + +/* USE_ROMLIB is not supported */ +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) + +/* Defined based on actual binary sizes */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0x0 +#define PLAT_ARM_MAX_BL2_SIZE 0x20000 +#define PLAT_ARM_MAX_BL31_SIZE 0x70000 + +#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) +#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) + +#define PLAT_CSS_MHU_BASE UL(0x2A920000) +#define PLAT_ARM_NSTIMER_FRAME_ID U(0) + +#define SOC_CSS_SEC_UART_BASE UL(0x2A410000) +#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) +#define SOC_CSS_UART_SIZE UL(0x10000) +#define SOC_CSS_UART_CLK_IN_HZ UL(7372800) +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ +#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +/* Physical and virtual address space limits for MMU */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE UL(0x30000000) +#define PLAT_ARM_GICR_BASE UL(0x301C0000) +#define PLAT_ARM_GICC_BASE UL(0x2C000000) +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +/* Virtual address used by dynamic mem_protect for chunk_base */ +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) + +/* Secure Watchdog Constants */ +#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) +#define SBSA_SECURE_WDOG_TIMEOUT UL(100) + +#define V2M_SYS_LED_SS_SHIFT U(0) +#define V2M_SYS_LED_EL_SHIFT U(1) +#define V2M_SYS_LED_EC_SHIFT U(3) + +#define V2M_SYS_LED_SS_MASK U(0x01) +#define V2M_SYS_LED_EL_MASK U(0x03) +#define V2M_SYS_LED_EC_MASK U(0x1f) + +#define V2M_SYSREGS_BASE UL(0x0C010000) +#define V2M_SYS_LED U(0x8) + +#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) +#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 +#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 + +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +#ifdef IMAGE_BL2 +#define PLAT_ARM_MMAP_ENTRIES U(5) +#else +#define PLAT_ARM_MMAP_ENTRIES U(6) +#endif +#define MAX_XLAT_TABLES U(6) + +#define V2M_FLASH0_BASE UL(0x08000000) +#define V2M_FLASH0_SIZE UL(0x04000000) +#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +/* RD1AE-specific memory mappings */ +#define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RO | \ + MT_SECURE) + +#define RD1AE_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \ + ARM_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | \ + MT_NS) + +#define RD1AE_DEVICE_BASE (0x20000000) +#define RD1AE_DEVICE_SIZE (0x20000000) +#define RD1AE_MAP_DEVICE MAP_REGION_FLAT(RD1AE_DEVICE_BASE, \ + RD1AE_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | \ + MT_SECURE) + +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - \ + V2M_FLASH_BLOCK_SIZE) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S new file mode 100644 index 000000000..32260efc7 --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl plat_arm_calc_core_pos + + /* --------------------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * + * Function to calculate the core position on rd1ae. + * + * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + + * (CPUId * PLAT_MAX_PE_PER_CPU) + + * ThreadId + * + * which can be simplified as: + * + * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- + */ +func plat_arm_calc_core_pos + mov x4, x0 + + /* Extract individual affinity fields from MPIDR */ + ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov x4, #PLAT_ARM_CLUSTER_COUNT + madd x2, x3, x4, x2 + mov x4, #PLAT_MAX_CPUS_PER_CLUSTER + madd x1, x2, x4, x1 + mov x4, #PLAT_MAX_PE_PER_CPU + madd x0, x1, x4, x0 + ret +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk new file mode 100644 index 000000000..d51622abc --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk @@ -0,0 +1,50 @@ +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# RD1AE (Kronos) platform. +$(info Platform ${PLAT} is (kronos) specific.) + +RD1AE_BASE = plat/arm/board/automotive_rd/platform/rd1ae + +PLAT_INCLUDES += -I${RD1AE_BASE}/include/ + +override ARM_PLAT_MT := 1 +override ARM_RECOM_STATE_ID_ENC := 1 +override CSS_LOAD_SCP_IMAGES := 0 +override CTX_INCLUDE_AARCH32_REGS := 0 +override ENABLE_SVE_FOR_NS := 1 +override ENABLE_SVE_FOR_SWD := 1 +override NEED_BL1 := 0 +override NEED_BL2U := 0 +override NEED_BL31 := 0 +override PSCI_EXTENDED_STATE_ID := 1 + +ARM_ARCH_MAJOR := 9 +ARM_ARCH_MINOR := 2 +CSS_USE_SCMI_SDS_DRIVER := 1 +ENABLE_FEAT_AMU := 1 +ENABLE_FEAT_ECV := 1 +ENABLE_FEAT_FGT := 1 +ENABLE_FEAT_MTE2 := 1 +ENABLE_MPAM_FOR_LOWER_ELS := 1 +HW_ASSISTED_COHERENCY := 1 +RESET_TO_BL2 := 1 +SVE_VECTOR_LEN := 128 +USE_COHERENT_MEM := 0 + +RD1AE_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S + +PLAT_BL_COMMON_SOURCES += ${RD1AE_BASE}/rd1ae_plat.c \ + ${RD1AE_BASE}/include/rd1ae_helpers.S + +BL2_SOURCES += ${RD1AE_CPU_SOURCES} \ + ${RD1AE_BASE}/rd1ae_err.c \ + lib/utils/mem_region.c \ + plat/arm/common/arm_nor_psci_mem_protect.c \ + drivers/arm/sbsa/sbsa.c + +include plat/arm/common/arm_common.mk +include plat/arm/css/common/css_common.mk +include plat/arm/board/common/board_common.mk diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c new file mode 100644 index 000000000..625447331 --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/* + * rd1ae error handler + */ +void __dead2 plat_arm_error_handler(int err) +{ + console_flush(); + + sbsa_wdog_refresh(SBSA_SECURE_WDOG_BASE); + + while (1) { + wfi(); + } +} diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c new file mode 100644 index 000000000..52d9c1f94 --- /dev/null +++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + RD1AE_MAP_DEVICE, + RD1AE_EXTERNAL_FLASH, +#if IMAGE_BL2 + RD1AE_MAP_NS_DRAM1, +#endif + {0} +}; + +void plat_arm_secure_wdt_start(void) +{ + sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); +} + +void plat_arm_secure_wdt_stop(void) +{ + sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); +} + +/* + * For rd1ae we should not do anything in these interface functions. + * They are used to override the weak functions in cci drivers + */ +void plat_arm_interconnect_init(void) +{ +} + +void plat_arm_interconnect_enter_coherency(void) +{ +} + +void plat_arm_interconnect_exit_coherency(void) +{ +} + +/* + * TZC programming is currently not done. + */ +void plat_arm_security_setup(void) +{ +}