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fix(cpus): workaround for Cortex X3 erratum 2743088

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Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instruction before the ISB of the powerdown code sequence specified in
the TRM.

SDEN documentation: https://developer.arm.com/documentation/2055130

Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This commit is contained in:
Harrison Mutai 2023-12-12 11:17:19 +00:00
parent 02091541d7
commit f43e9f57dc
4 changed files with 20 additions and 3 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -775,6 +775,10 @@ For Cortex-X3, the following errata build flags are defined :
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2. r1p1. It is fixed in r1p2.
- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is
fixed in r1p2.
- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 - ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2. CPU. It is fixed in r1p2.

8
lib/cpus/aarch64/cortex_x3.S
View file

@ -57,6 +57,13 @@ workaround_reset_end cortex_x3, ERRATUM(2742421)
check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
/* dsb before isb of power down sequence */
dsb sy
workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
/* Set CPUACTLR3_EL1 bit 47 */ /* Set CPUACTLR3_EL1 bit 47 */
sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
@ -88,6 +95,7 @@ apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
* --------------------------------------------------- * ---------------------------------------------------
*/ */
sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
isb isb
ret ret
endfunc cortex_x3_core_pwr_dwn endfunc cortex_x3_core_pwr_dwn

4
lib/cpus/cpu-ops.mk
View file

@ -777,6 +777,10 @@ CPU_FLAG_LIST += ERRATA_X3_2615812
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2742421 CPU_FLAG_LIST += ERRATA_X3_2742421
# Flag to apply erratum 2743088 workaround on powerdown. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2743088
# Flag to apply erratum 2779509 workaround on reset. This erratum applies # Flag to apply erratum 2779509 workaround on reset. This erratum applies
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2779509 CPU_FLAG_LIST += ERRATA_X3_2779509

5
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -447,8 +447,9 @@ struct em_cpu_list cpu_list[] = {
[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, [1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, [2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, [3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
[4] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, [4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
[5 ... ERRATA_LIST_END] = UNDEF_ERRATA, [5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* CORTEX_X3_H_INC */ #endif /* CORTEX_X3_H_INC */