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refactor(mt8195): use ptp3 common drivers

Browse source 
Some 8195 ptp3 drivers are the same in plat/mediatek/drivers/ptp3, so
add this patch to reuse them.

Change-Id: I2b1801a73b6a2979e20d49d314c57f663dc5bf04
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
This commit is contained in:
Liju-Clr Chen 2022-11-03 19:49:23 +08:00
parent 44a10511c9
commit f278d84ded
5 changed files with 52 additions and 194 deletions
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52
plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
View file

@ -1,52 +0,0 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_PTP3_COMMON_H
#define MTK_PTP3_COMMON_H
#include <lib/mmio.h>
#include <lib/utils_def.h>
/************************************************
* CPU info
************************************************/
#define NR_PTP3_CFG_CPU U(8)
#define PTP3_CFG_CPU_START_ID_L U(0)
#define PTP3_CFG_CPU_START_ID_B U(4)
#define PTP3_CFG_CPU_END_ID U(7)
#define NR_PTP3_CFG1_DATA U(2)
#define PTP3_CFG1_MASK 0x3000
#define NR_PTP3_CFG2_DATA U(5)
#define PTP3_CFG3_MASK1 0x1180
#define PTP3_CFG3_MASK2 0x35C0
#define PTP3_CFG3_MASK3 0x3DC0
/************************************************
* register read/write
************************************************/
#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
#define ptp3_clrsetbits(addr, clear, set) \
mmio_clrsetbits_32((uintptr_t)addr, clear, set)
/************************************************
* config enum
************************************************/
enum PTP3_CFG {
PTP3_CFG_ADDR,
PTP3_CFG_VALUE,
NR_PTP3_CFG,
};
/************************************
* prototype
************************************/
extern void ptp3_core_init(unsigned int core);
extern void ptp3_core_unInit(unsigned int core);
#endif /* MTK_PTP3_COMMON_H */

137
plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
View file

@ -1,137 +0,0 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved. \
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <mtk_ptp3_common.h>
#define PTP3_CORE_OFT(core) (0x800 * (core))
/************************************************
* Central control
************************************************/
static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
{0x0C53A2A0, 0x1000},
{0x0C53A2A4, 0x1000}
};
static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
{0x0C530404, 0x3A1000},
{0x0C530428, 0x13E0408},
{0x0C530434, 0xB22800},
{0x0C53043C, 0x750},
{0x0C530440, 0x0222c4cc}
};
static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
static void ptp3_init(unsigned int core)
{
unsigned int i, addr, value;
if (core < PTP3_CFG_CPU_START_ID_B) {
ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
ptp3_cfg1[0][PTP3_CFG_VALUE]);
} else {
ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
ptp3_cfg1[1][PTP3_CFG_VALUE]);
}
if (core < PTP3_CFG_CPU_START_ID_B) {
for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
PTP3_CORE_OFT(core);
value = ptp3_cfg2[i][PTP3_CFG_VALUE];
ptp3_write(addr, value);
}
} else {
for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
PTP3_CORE_OFT(core);
if (i == 2) {
value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0;
} else {
value = ptp3_cfg2[i][PTP3_CFG_VALUE];
}
ptp3_write(addr, value);
}
}
if (core < PTP3_CFG_CPU_START_ID_B) {
addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
value = ptp3_cfg3[PTP3_CFG_VALUE];
ptp3_write(addr, value & PTP3_CFG3_MASK1);
ptp3_write(addr, value & PTP3_CFG3_MASK2);
ptp3_write(addr, value & PTP3_CFG3_MASK3);
} else {
addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
value = ptp3_cfg3_ext[PTP3_CFG_VALUE];
ptp3_write(addr, value & PTP3_CFG3_MASK1);
ptp3_write(addr, value & PTP3_CFG3_MASK2);
ptp3_write(addr, value & PTP3_CFG3_MASK3);
}
}
void pdp_proc_ARM_write(unsigned int pdp_n)
{
unsigned long v = 0;
dsb();
__asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
v |= (UL(0x0) << 52);
v |= (UL(0x1) << 53);
v |= (UL(0x0) << 54);
v |= (UL(0x0) << 48);
v |= (UL(0x1) << 49);
__asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
dsb();
}
void pdp_init(unsigned int pdp_cpu, unsigned int en)
{
if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) &&
(pdp_cpu < NR_PTP3_CFG_CPU)) {
pdp_proc_ARM_write(pdp_cpu);
}
}
static void dt_proc_ARM_write(unsigned int dt_n)
{
unsigned long v = 0;
dsb();
__asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
v |= (UL(0x0) << 33);
v |= (UL(0x0) << 32);
__asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
dsb();
}
void dt_init(unsigned int dt_cpu, unsigned int en)
{
if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) &&
(dt_cpu < NR_PTP3_CFG_CPU)) {
dt_proc_ARM_write(dt_cpu);
}
}
void ptp3_core_init(unsigned int core)
{
/* init for ptp3 */
ptp3_init(core);
/* init for pdp */
pdp_init(core, 1);
/* init for dt */
dt_init(core, 1);
}
void ptp3_core_unInit(unsigned int core)
{
/* TBD */
}

46
plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h Normal file
View file

@ -0,0 +1,46 @@
/*
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PTP3_PLAT_H
#define PTP3_PLAT_H
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <ptp3_common.h>
/* CPU info */
#define NR_PTP3_CFG_CPU U(8)
#define PTP3_CFG_CPU_START_ID_L U(0)
#define PTP3_CFG_CPU_START_ID_B U(4)
#define PTP3_CFG_CPU_END_ID U(7)
#define NR_PTP3_CFG1_DATA U(2)
#define PTP3_CFG1_MASK 0x3000
#define NR_PTP3_CFG2_DATA U(5)
#define PTP3_CFG3_MASK1 0x1180
#define PTP3_CFG3_MASK2 0x35C0
#define PTP3_CFG3_MASK3 0x3DC0
/* Central control */
static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
{0x0C53A2A0, 0x1000},
{0x0C53A2A4, 0x1000}
};
static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
{0x0C530404, 0x3A1000},
{0x0C530428, 0x13E0408},
{0x0C530434, 0xB22800},
{0x0C53043C, 0x750},
{0x0C530440, 0x0222c4cc}
};
static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
#endif /* PTP3_PLAT_H */

8
plat/mediatek/mt8195/plat_pm.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,15 +13,15 @@
#include <lib/psci/psci.h>
/* platform specific headers */
#include <mt_gic_v3.h>
#include <mtk_ptp3_common.h>
#include <mtspmc.h>
#include <plat/common/platform.h>
#include <mt_gic_v3.h>
#include <mtspmc.h>
#include <plat_dfd.h>
#include <plat_mtk_lpm.h>
#include <plat_params.h>
#include <plat_pm.h>
#include <pmic.h>
#include <ptp3_common.h>
#include <rtc.h>
/*

3
plat/mediatek/mt8195/platform.mk
View file

@ -15,6 +15,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/drivers/gpio/ \
-I${MTK_PLAT}/drivers/pmic/ \
-I${MTK_PLAT}/drivers/pmic_wrap/ \
-I${MTK_PLAT}/drivers/ptp3/ \
-I${MTK_PLAT}/drivers/rtc/ \
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
@ -59,6 +60,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT}/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/drivers/pmic/pmic.c \
${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c \
${MTK_PLAT}/drivers/ptp3/ptp3_common.c \
${MTK_PLAT}/drivers/rtc/rtc_common.c \
${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c \
${MTK_PLAT}/drivers/timer/mt_timer.c \
@ -79,7 +81,6 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \