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feat(arm): enable FHI PPI interrupt to report CPU errors
To handle the core corrected errors in the firmware, the FHI PPI interrupt has to be enabled on all the cores. At boot, when the RAS framework is initialized, only primary core is up and hence core FHI PPI interrupt is enabled only on primary core. This patch adds support to configure and enable core FHI interrupt for all the secondary cores as part of their boot sequence. Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656
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2 changed files with 8 additions and 1 deletions
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@ -782,6 +782,9 @@ MEASURED_BOOT
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#define PLAT_SDEI_CRITICAL_PRI 0x60
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#define PLAT_SDEI_CRITICAL_PRI 0x60
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#define PLAT_SDEI_NORMAL_PRI 0x70
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#define PLAT_SDEI_NORMAL_PRI 0x70
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/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
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#define PLAT_CORE_FAULT_IRQ 17
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/* ARM platforms use 3 upper bits of secure interrupt priority */
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/* ARM platforms use 3 upper bits of secure interrupt priority */
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#define PLAT_PRI_BITS 3
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#define PLAT_PRI_BITS 3
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@ -40,7 +40,11 @@ static const uintptr_t *gicr_frames = gicr_base_addrs;
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static const interrupt_prop_t arm_interrupt_props[] = {
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static const interrupt_prop_t arm_interrupt_props[] = {
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PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
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PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
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#if RAS_FFH_SUPPORT
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INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
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GIC_INTR_CFG_LEVEL)
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#endif
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};
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};
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/*
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/*
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