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fix(arm): fix GIC macros for GICv4.1 support

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Newer platforms such as Neoverse V2 with GICv4.1 will report
0x3 instead of 0x1 in ID_AA64PFR0_EL1.

Update the logic to not accidentially take the GICv2 path
when printing the GIC registers.

Change-Id: Ia0d546cc5dcaa0dcad49a75b5921b0df5e176d34
Signed-off-by: Moritz Fischer <moritzf@google.com>
This commit is contained in:
Moritz Fischer 2023-10-18 16:16:33 +00:00
parent 0efa651234
commit f1df8f10c6
1 changed files with 9 additions and 3 deletions
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12
include/plat/arm/common/aarch64/arm_macros.S
View file

@ -39,11 +39,17 @@ prefix:
* ---------------------------------------------
*/
.macro arm_print_gic_regs
/* Check for GICv3 system register access */
/* Check for GICv3/v4 system register access.
* ID_AA64PFR0_GIC indicates presence of the CPU
* system registers by either 0b0011 or 0xb0001.
* A value of 0b000 means CPU system registers aren't
* available and the code needs to use the memory
* mapped registers like in GICv2.
*/
mrs x7, id_aa64pfr0_el1
ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
cmp x7, #1
b.ne print_gicv2
cmp x7, #0
b.eq print_gicv2
/* Check for SRE enable */
mrs x8, ICC_SRE_EL3