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fix(errata): workaround for Neoverse-N2 erratum 2138953

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Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
This commit is contained in:
nayanpatel-arm 2021-09-28 09:46:45 -07:00
parent ab5964aadc
commit ef8f0c52dd
4 changed files with 67 additions and 13 deletions
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3
docs/design/cpu-specific-build-macros.rst
View file

@ -403,6 +403,9 @@ For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 - ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
DSU Errata Workarounds DSU Errata Workarounds
---------------------- ----------------------

8
include/lib/cpus/aarch64/neoverse_n2.h
View file

@ -41,4 +41,12 @@
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#endif /* NEOVERSE_N2_H */ #endif /* NEOVERSE_N2_H */

35
lib/cpus/aarch64/neoverse_n2.S
View file

@ -183,6 +183,35 @@ func check_errata_2138956
b cpu_rev_var_ls b cpu_rev_var_ls
endfunc check_errata_2138956 endfunc check_errata_2138956
/* --------------------------------------------------
* Errata Workaround for Neoverse N2 Erratum 2138953.
* This applies to revision r0p0 of Neoverse N2. it is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_n2_2138953_wa
/* Check revision. */
mov x17, x30
bl check_errata_2138953
cbz x0, 1f
/* Apply instruction patching sequence */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
msr NEOVERSE_N2_CPUECTLR2_EL1, x1
1:
ret x17
endfunc errata_n2_2138953_wa
func check_errata_2138953
/* Applies to r0p0 */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_2138953
/* ------------------------------------------- /* -------------------------------------------
* The CPU Ops reset function for Neoverse N2. * The CPU Ops reset function for Neoverse N2.
* ------------------------------------------- * -------------------------------------------
@ -224,6 +253,11 @@ func neoverse_n2_reset_func
bl errata_n2_2138956_wa bl errata_n2_2138956_wa
#endif #endif
#if ERRATA_N2_2138953
mov x0, x18
bl errata_n2_2138953_wa
#endif
#if ENABLE_AMU #if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, cptr_el3 mrs x0, cptr_el3
@ -289,6 +323,7 @@ func neoverse_n2_errata_report
report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
ldp x8, x30, [sp], #16 ldp x8, x30, [sp], #16
ret ret

8
lib/cpus/cpu-ops.mk
View file

@ -441,6 +441,10 @@ ERRATA_N2_2189731 ?=0
# to revision r0p0 of the Neoverse N2 cpu and is still open. # to revision r0p0 of the Neoverse N2 cpu and is still open.
ERRATA_N2_2138956 ?=0 ERRATA_N2_2138956 ?=0
# Flag to apply erratum 2138953 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is still open.
ERRATA_N2_2138953 ?=0
# Flag to apply erratum 2055002 workaround during reset. This erratum applies # Flag to apply erratum 2055002 workaround during reset. This erratum applies
# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_2055002 ?=0 ERRATA_A710_2055002 ?=0
@ -822,6 +826,10 @@ $(eval $(call add_define,ERRATA_N2_2189731))
$(eval $(call assert_boolean,ERRATA_N2_2138956)) $(eval $(call assert_boolean,ERRATA_N2_2138956))
$(eval $(call add_define,ERRATA_N2_2138956)) $(eval $(call add_define,ERRATA_N2_2138956))
# Process ERRATA_N2_2138953 flag
$(eval $(call assert_boolean,ERRATA_N2_2138953))
$(eval $(call add_define,ERRATA_N2_2138953))
# Process ERRATA_A710_2055002 flag # Process ERRATA_A710_2055002 flag
$(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call assert_boolean,ERRATA_A710_2055002))
$(eval $(call add_define,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002))