diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 72ffbe279..f787ebcc0 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -15,7 +15,6 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX -#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* 1 = Flush cache, 0 = No cache flush. * Default for Agilex is No cache flush. * For Agilex FP8, set to Flush cache. diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 21cc6a3c0..9ff80399d 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -87,6 +87,24 @@ $(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) +# Configs for Boot Source +SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 +SOCFPGA_BOOT_SOURCE_QSPI ?= 0 +SOCFPGA_BOOT_SOURCE_NAND ?= 0 + +$(eval $(call assert_booleans,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) +$(eval $(call add_defines,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) + # Configs for VAB Authentication SOCFPGA_SECURE_VAB_AUTH := 0 $(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH)) diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h index ab6e2bcba..31d28f27c 100644 --- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h @@ -16,7 +16,6 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 -#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* 1 = Flush cache, 0 = No cache flush. * Default for Agilex5 is Cache flush. */ diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk index 4bb90d5a5..172b554f5 100644 --- a/plat/intel/soc/agilex5/platform.mk +++ b/plat/intel/soc/agilex5/platform.mk @@ -113,6 +113,24 @@ $(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) +# Configs for Boot Source +SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 +SOCFPGA_BOOT_SOURCE_QSPI ?= 0 +SOCFPGA_BOOT_SOURCE_NAND ?= 0 + +$(eval $(call assert_booleans,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) +$(eval $(call add_defines,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) + # Configs for VAB Authentication SOCFPGA_SECURE_VAB_AUTH := 0 $(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH)) diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 0788ab8bd..f3fb1a4a4 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -22,6 +22,18 @@ #define PLAT_SOCFPGA_AGILEX5 4 #define SIMICS_RUN 1 #define MAX_IO_MTD_DEVICES U(1) +/* Boot Source configuration + * TODO: Shall consider "assert_numeric" in the future + */ +#if SOCFPGA_BOOT_SOURCE_NAND +#define BOOT_SOURCE BOOT_SOURCE_NAND +#elif SOCFPGA_BOOT_SOURCE_SDMMC +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#elif SOCFPGA_BOOT_SOURCE_QSPI +#define BOOT_SOURCE BOOT_SOURCE_QSPI +#else +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#endif /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index a0d4180ae..fbe18c3e3 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -24,8 +24,8 @@ typedef enum { BOOT_SOURCE_FPGA = 0, BOOT_SOURCE_SDMMC, BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI + BOOT_SOURCE_QSPI, + BOOT_SOURCE_RSVD } boot_source_type; /******************************************************************************* diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h index c5e66c743..cbaccfd72 100644 --- a/plat/intel/soc/n5x/include/socfpga_plat_def.h +++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h @@ -15,7 +15,6 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_N5X -#define BOOT_SOURCE BOOT_SOURCE_SDMMC #define PLAT_PRIMARY_CPU 0 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index 29fd0eb28..4770f8d3e 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -1,5 +1,6 @@ # -# Copyright (c) 2020-2022, Intel Corporation. All rights reserved. +# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. +# Copyright (c) 2024, Altera Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -46,8 +47,30 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c +# Don't have the Linux kernel as a BL33 image by default +ARM_LINUX_KERNEL_AS_BL33 := 0 +$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) +# Configs for Boot Source +SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 +SOCFPGA_BOOT_SOURCE_QSPI ?= 0 +SOCFPGA_BOOT_SOURCE_NAND ?= 0 + +$(eval $(call assert_booleans,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) +$(eval $(call add_defines,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) + PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index cd4c1633f..35b92c5f1 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -14,7 +14,6 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 -#define BOOT_SOURCE BOOT_SOURCE_SDMMC #define PLAT_PRIMARY_CPU 0 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 0a33c3d68..4cd7032e1 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -78,8 +78,30 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c +# Don't have the Linux kernel as a BL33 image by default +ARM_LINUX_KERNEL_AS_BL33 := 0 +$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) +# Configs for Boot Source +SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 +SOCFPGA_BOOT_SOURCE_QSPI ?= 0 +SOCFPGA_BOOT_SOURCE_NAND ?= 0 + +$(eval $(call assert_booleans,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) +$(eval $(call add_defines,\ + $(sort \ + SOCFPGA_BOOT_SOURCE_SDMMC \ + SOCFPGA_BOOT_SOURCE_QSPI \ + SOCFPGA_BOOT_SOURCE_NAND \ +))) + PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 USE_COHERENT_MEM := 1