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docs: marvell: update build instructions with CN913x
Add references to the OcteonTX2 CN913x family. Change-Id: I172a8e3d061086bf4843acad014c113c80359e01 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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1 changed files with 16 additions and 6 deletions
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@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin``
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*u-boot.bin* should be used and not *u-boot-spl.bin*
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*u-boot.bin* should be used and not *u-boot-spl.bin*
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Set MSS/SCP image path (mandatory only for Armada80x0)
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Set MSS/SCP image path (mandatory only for A7K/8K/CN913x)
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.. code:: shell
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.. code:: shell
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@ -92,22 +92,31 @@ There are several build options:
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- BLE_PATH
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- BLE_PATH
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Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
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Points to BLE (Binary ROM extension) sources folder.
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Only required for A7K/8K/CN913x builds.
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The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``.
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The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``.
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- MV_DDR_PATH
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- MV_DDR_PATH
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For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
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For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
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it is used for ddr_tool build.
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it is used for ddr_tool build.
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Usage example: MV_DDR_PATH=path/to/mv_ddr
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Usage example: MV_DDR_PATH=path/to/mv_ddr
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The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
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The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr
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sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
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sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
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is necessary for A37x0.
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is necessary for A37x0.
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For the mv_ddr source location, check the section "Tools and external components installation"
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For the mv_ddr source location, check the section "Tools and external components installation"
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- CP_NUM
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Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
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the build uses the default number of CPs, which is a number of embedded CPs inside the
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package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC
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family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid
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values with CP_NUM are in a range of 1 to 3.
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- DDR_TOPOLOGY
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- DDR_TOPOLOGY
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For Armada37x0 only, the DDR topology map index/name, default is 0.
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For Armada37x0 only, the DDR topology map index/name, default is 0.
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@ -191,7 +200,8 @@ There are several build options:
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- a70x0
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- a70x0
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- a70x0_amc (for AMC board)
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- a70x0_amc (for AMC board)
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- a80x0
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- a80x0
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- a80x0_mcbin (for MacciatoBin)
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- a80x0_mcbin (for MacchiatoBin)
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- t9130 (OcteonTX2 CN913x)
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Special Build Flags
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Special Build Flags
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--------------------
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--------------------
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@ -199,7 +209,7 @@ Special Build Flags
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- PLAT_RECOVERY_IMAGE_ENABLE
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- PLAT_RECOVERY_IMAGE_ENABLE
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When set this option to enable secondary recovery function when build atf.
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When set this option to enable secondary recovery function when build atf.
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In order to build UART recovery image this operation should be disabled for
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In order to build UART recovery image this operation should be disabled for
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a70x0 and a80x0 because of hardware limitation (boot from secondary image
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A7K/8K/CN913x because of hardware limitation (boot from secondary image
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can interrupt UART recovery process). This MACRO definition is set in
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can interrupt UART recovery process). This MACRO definition is set in
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``plat/marvell/armada/a8k/common/include/platform_def.h`` file.
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``plat/marvell/armada/a8k/common/include/platform_def.h`` file.
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