Remove early_exceptions from BL3-1

The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.

Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
This commit is contained in:
Andrew Thoelke 2014-06-02 12:38:12 +01:00
parent 5e91007424
commit ee94cc6fa6
7 changed files with 9 additions and 40 deletions

View file

@ -72,11 +72,13 @@ func bl31_entrypoint
isb isb
/* --------------------------------------------- /* ---------------------------------------------
* Set the exception vector to something sane. * Set the exception vector and zero tpidr_el3
* until the crash reporting is set up
* --------------------------------------------- * ---------------------------------------------
*/ */
adr x1, early_exceptions adr x1, runtime_exceptions
msr vbar_el3, x1 msr vbar_el3, x1
msr tpidr_el3, xzr
/* --------------------------------------------------------------------- /* ---------------------------------------------------------------------
* The initial state of the Architectural feature trap register * The initial state of the Architectural feature trap register
@ -134,10 +136,10 @@ func bl31_entrypoint
* Initialise cpu_data and crash reporting * Initialise cpu_data and crash reporting
* --------------------------------------------- * ---------------------------------------------
*/ */
bl init_cpu_data_ptr
#if CRASH_REPORTING #if CRASH_REPORTING
bl init_crash_reporting bl init_crash_reporting
#endif #endif
bl init_cpu_data_ptr
/* --------------------------------------------- /* ---------------------------------------------
* Use SP_EL0 for the C runtime stack. * Use SP_EL0 for the C runtime stack.

View file

@ -39,7 +39,6 @@ BL31_SOURCES += bl31/bl31_main.c \
bl31/aarch64/cpu_data.S \ bl31/aarch64/cpu_data.S \
bl31/aarch64/runtime_exceptions.S \ bl31/aarch64/runtime_exceptions.S \
bl31/aarch64/crash_reporting.S \ bl31/aarch64/crash_reporting.S \
common/aarch64/early_exceptions.S \
lib/aarch64/cpu_helpers.S \ lib/aarch64/cpu_helpers.S \
lib/locks/bakery/bakery_lock.c \ lib/locks/bakery/bakery_lock.c \
lib/locks/exclusive/spinlock.S \ lib/locks/exclusive/spinlock.S \

View file

@ -71,7 +71,6 @@ void bl31_lib_init()
******************************************************************************/ ******************************************************************************/
void bl31_main(void) void bl31_main(void)
{ {
/* Perform remaining generic architectural setup from EL3 */ /* Perform remaining generic architectural setup from EL3 */
bl31_arch_setup(); bl31_arch_setup();
@ -89,16 +88,7 @@ void bl31_main(void)
/* Clean caches before re-entering normal world */ /* Clean caches before re-entering normal world */
dcsw_op_all(DCCSW); dcsw_op_all(DCCSW);
/* /* By default run the non-secure BL3-3 image next */
* Use the more complex exception vectors now that context
* management is setup. SP_EL3 should point to a 'cpu_context'
* structure which has an exception stack allocated. The PSCI
* service should have set the context.
*/
assert(cm_get_context(NON_SECURE));
cm_set_next_eret_context(NON_SECURE);
write_vbar_el3((uint64_t) runtime_exceptions);
isb();
next_image_type = NON_SECURE; next_image_type = NON_SECURE;
/* /*

View file

@ -268,7 +268,6 @@ void runtime_svc_init();
extern uint64_t __RT_SVC_DESCS_START__; extern uint64_t __RT_SVC_DESCS_START__;
extern uint64_t __RT_SVC_DESCS_END__; extern uint64_t __RT_SVC_DESCS_END__;
void init_crash_reporting(void); void init_crash_reporting(void);
void runtime_exceptions(void);
#endif /*__ASSEMBLY__*/ #endif /*__ASSEMBLY__*/
#endif /* __RUNTIME_SVC_H__ */ #endif /* __RUNTIME_SVC_H__ */

View file

@ -372,16 +372,6 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
*/ */
bl31_arch_setup(); bl31_arch_setup();
/*
* Use the more complex exception vectors to enable SPD
* initialisation. SP_EL3 should point to a 'cpu_context'
* structure. The calling cpu should have set the
* context already
*/
assert(cm_get_context(NON_SECURE));
cm_set_next_eret_context(NON_SECURE);
write_vbar_el3((uint64_t) runtime_exceptions);
/* /*
* Call the cpu on finish handler registered by the Secure Payload * Call the cpu on finish handler registered by the Secure Payload
* Dispatcher to let it do any bookeeping. If the handler encounters an * Dispatcher to let it do any bookeeping. If the handler encounters an

View file

@ -490,15 +490,6 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr,
cm_el3_sysregs_context_restore(NON_SECURE); cm_el3_sysregs_context_restore(NON_SECURE);
rc = PSCI_E_SUCCESS; rc = PSCI_E_SUCCESS;
/*
* Use the more complex exception vectors to enable SPD
* initialisation. SP_EL3 should point to a 'cpu_context'
* structure. The non-secure context should have been
* set on this cpu prior to suspension.
*/
cm_set_next_eret_context(NON_SECURE);
write_vbar_el3((uint64_t) runtime_exceptions);
/* /*
* Call the cpu suspend finish handler registered by the Secure Payload * Call the cpu suspend finish handler registered by the Secure Payload
* Dispatcher to let it do any bookeeping. If the handler encounters an * Dispatcher to let it do any bookeeping. If the handler encounters an

View file

@ -67,12 +67,10 @@ psci_aff_common_finish_entry:
bl init_cpu_data_ptr bl init_cpu_data_ptr
/* --------------------------------------------- /* ---------------------------------------------
* Exceptions should not occur at this point. * Set the exception vectors
* Set VBAR in order to handle and report any
* that do occur
* --------------------------------------------- * ---------------------------------------------
*/ */
adr x0, early_exceptions adr x0, runtime_exceptions
msr vbar_el3, x0 msr vbar_el3, x0
isb isb