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Remove early_exceptions from BL3-1
The crash reporting support and early initialisation of the cpu_data allow the runtime_exception vectors to be used from the start in BL3-1, removing the need for the additional early_exception vectors and 2KB of code from BL3-1. Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
This commit is contained in:
parent
5e91007424
commit
ee94cc6fa6
7 changed files with 9 additions and 40 deletions
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@ -72,11 +72,13 @@ func bl31_entrypoint
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isb
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* Set the exception vector and zero tpidr_el3
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* until the crash reporting is set up
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* ---------------------------------------------
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*/
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adr x1, early_exceptions
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adr x1, runtime_exceptions
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msr vbar_el3, x1
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msr tpidr_el3, xzr
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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@ -134,10 +136,10 @@ func bl31_entrypoint
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* Initialise cpu_data and crash reporting
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* ---------------------------------------------
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*/
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bl init_cpu_data_ptr
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#if CRASH_REPORTING
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bl init_crash_reporting
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#endif
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bl init_cpu_data_ptr
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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@ -38,8 +38,7 @@ BL31_SOURCES += bl31/bl31_main.c \
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bl31/aarch64/context.S \
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bl31/aarch64/cpu_data.S \
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bl31/aarch64/runtime_exceptions.S \
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bl31/aarch64/crash_reporting.S \
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common/aarch64/early_exceptions.S \
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bl31/aarch64/crash_reporting.S \
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lib/aarch64/cpu_helpers.S \
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lib/locks/bakery/bakery_lock.c \
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lib/locks/exclusive/spinlock.S \
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@ -71,7 +71,6 @@ void bl31_lib_init()
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******************************************************************************/
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void bl31_main(void)
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{
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/* Perform remaining generic architectural setup from EL3 */
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bl31_arch_setup();
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@ -89,16 +88,7 @@ void bl31_main(void)
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/* Clean caches before re-entering normal world */
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dcsw_op_all(DCCSW);
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/*
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* Use the more complex exception vectors now that context
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* management is setup. SP_EL3 should point to a 'cpu_context'
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* structure which has an exception stack allocated. The PSCI
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* service should have set the context.
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*/
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assert(cm_get_context(NON_SECURE));
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cm_set_next_eret_context(NON_SECURE);
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write_vbar_el3((uint64_t) runtime_exceptions);
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isb();
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/* By default run the non-secure BL3-3 image next */
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next_image_type = NON_SECURE;
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/*
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@ -268,7 +268,6 @@ void runtime_svc_init();
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extern uint64_t __RT_SVC_DESCS_START__;
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extern uint64_t __RT_SVC_DESCS_END__;
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void init_crash_reporting(void);
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void runtime_exceptions(void);
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#endif /*__ASSEMBLY__*/
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#endif /* __RUNTIME_SVC_H__ */
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@ -372,16 +372,6 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
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*/
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bl31_arch_setup();
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/*
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* Use the more complex exception vectors to enable SPD
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* initialisation. SP_EL3 should point to a 'cpu_context'
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* structure. The calling cpu should have set the
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* context already
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*/
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assert(cm_get_context(NON_SECURE));
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cm_set_next_eret_context(NON_SECURE);
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write_vbar_el3((uint64_t) runtime_exceptions);
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/*
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* Call the cpu on finish handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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@ -490,15 +490,6 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr,
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cm_el3_sysregs_context_restore(NON_SECURE);
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rc = PSCI_E_SUCCESS;
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/*
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* Use the more complex exception vectors to enable SPD
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* initialisation. SP_EL3 should point to a 'cpu_context'
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* structure. The non-secure context should have been
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* set on this cpu prior to suspension.
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*/
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cm_set_next_eret_context(NON_SECURE);
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write_vbar_el3((uint64_t) runtime_exceptions);
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/*
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* Call the cpu suspend finish handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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@ -67,12 +67,10 @@ psci_aff_common_finish_entry:
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bl init_cpu_data_ptr
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/* ---------------------------------------------
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* Exceptions should not occur at this point.
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* Set VBAR in order to handle and report any
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* that do occur
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* Set the exception vectors
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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adr x0, runtime_exceptions
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msr vbar_el3, x0
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isb
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