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aarch32: Fix multiple bugs in amu_helpers.S
AArch32 uses odd-even pairs when passing 64-bit arguments to functions. For example in `amu_group0_cnt_write_internal()` the second argument is a uint64_t which is passed in r2 and r3. In `amu_group1_set_evtype_internal()` the value that needs to be written to the system register is in r1 not in r0. Change-Id: I20196268fdb1dc9ef6c4ebe61e761fba9623b3f2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This commit is contained in:
Dimitris Papastamos
parent
e6e17ee8f1
commit
edea5c124d
1 changed files with 89 additions and 85 deletions
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@ -18,7 +18,7 @@
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* uint64_t amu_group0_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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* and return it in `r0` and `r1`.
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*/
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func amu_group0_cnt_read_internal
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#if ENABLE_ASSERTIONS
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@ -52,13 +52,15 @@ endfunc amu_group0_cnt_read_internal
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* void amu_group0_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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* `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
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* `r1` is used as a scratch register.
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*/
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func amu_group0_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 3] */
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mov r2, r0
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lsr r2, r2, #2
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #2
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -66,19 +68,19 @@ func amu_group0_cnt_write_internal
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* Given `idx` calculate address of stcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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adr r1, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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add r1, r1, r0
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bx r1
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1:
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stcopr16 r0,r1, AMEVCNTR00 /* index 0 */
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stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR01 /* index 1 */
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stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR02 /* index 2 */
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stcopr16 r2, r3, AMEVCNTR02 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR03 /* index 3 */
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stcopr16 r2, r3, AMEVCNTR03 /* index 3 */
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bx lr
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endfunc amu_group0_cnt_write_internal
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@ -86,14 +88,14 @@ endfunc amu_group0_cnt_write_internal
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* uint64_t amu_group1_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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* and return it in `r0` and `r1`.
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*/
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func amu_group1_cnt_read_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #4
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -107,51 +109,53 @@ func amu_group1_cnt_read_internal
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bx r1
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1:
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ldcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR10 /* index 0 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR11 /* index 1 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR12 /* index 2 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR13 /* index 3 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR14 /* index 4 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR15 /* index 5 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR16 /* index 6 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR17 /* index 7 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR18 /* index 8 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR19 /* index 9 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1A /* index 10 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1B /* index 11 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1C /* index 12 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1D /* index 13 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1E /* index 14 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_read_internal
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/*
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* void amu_group1_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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* `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
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* `r1` is used as a scratch register.
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*/
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func amu_group1_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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mov r1, r0
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lsr r1, r1, #4
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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@ -159,43 +163,43 @@ func amu_group1_cnt_write_internal
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* Given `idx` calculate address of ldcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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adr r1, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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add r1, r1, r0
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bx r1
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1:
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stcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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stcopr16 r2, r3, AMEVCNTR16 /* index 6 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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stcopr16 r2, r3, AMEVCNTR17 /* index 7 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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stcopr16 r2, r3, AMEVCNTR18 /* index 8 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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stcopr16 r2, r3, AMEVCNTR19 /* index 9 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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stcopr16 r2, r3, AMEVCNTR1A /* index 10 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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stcopr16 r2, r3, AMEVCNTR1B /* index 11 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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stcopr16 r2, r3, AMEVCNTR1C /* index 12 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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stcopr16 r2, r3, AMEVCNTR1D /* index 13 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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stcopr16 r2, r3, AMEVCNTR1E /* index 14 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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stcopr16 r2, r3, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_write_internal
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@ -230,36 +234,36 @@ func amu_group1_set_evtype_internal
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bx r2
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1:
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stcopr r0, AMEVTYPER10 /* index 0 */
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stcopr r1, AMEVTYPER10 /* index 0 */
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bx lr
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stcopr r0, AMEVTYPER11 /* index 1 */
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stcopr r1, AMEVTYPER11 /* index 1 */
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bx lr
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stcopr r0, AMEVTYPER12 /* index 2 */
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stcopr r1, AMEVTYPER12 /* index 2 */
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bx lr
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stcopr r0, AMEVTYPER13 /* index 3 */
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stcopr r1, AMEVTYPER13 /* index 3 */
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bx lr
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stcopr r0, AMEVTYPER14 /* index 4 */
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stcopr r1, AMEVTYPER14 /* index 4 */
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bx lr
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stcopr r0, AMEVTYPER15 /* index 5 */
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stcopr r1, AMEVTYPER15 /* index 5 */
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bx lr
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stcopr r0, AMEVTYPER16 /* index 6 */
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stcopr r1, AMEVTYPER16 /* index 6 */
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bx lr
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stcopr r0, AMEVTYPER17 /* index 7 */
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stcopr r1, AMEVTYPER17 /* index 7 */
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bx lr
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stcopr r0, AMEVTYPER18 /* index 8 */
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stcopr r1, AMEVTYPER18 /* index 8 */
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bx lr
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stcopr r0, AMEVTYPER19 /* index 9 */
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stcopr r1, AMEVTYPER19 /* index 9 */
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bx lr
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stcopr r0, AMEVTYPER1A /* index 10 */
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stcopr r1, AMEVTYPER1A /* index 10 */
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bx lr
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stcopr r0, AMEVTYPER1B /* index 11 */
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stcopr r1, AMEVTYPER1B /* index 11 */
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bx lr
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stcopr r0, AMEVTYPER1C /* index 12 */
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stcopr r1, AMEVTYPER1C /* index 12 */
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bx lr
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stcopr r0, AMEVTYPER1D /* index 13 */
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stcopr r1, AMEVTYPER1D /* index 13 */
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bx lr
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stcopr r0, AMEVTYPER1E /* index 14 */
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stcopr r1, AMEVTYPER1E /* index 14 */
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bx lr
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stcopr r0, AMEVTYPER1F /* index 15 */
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stcopr r1, AMEVTYPER1F /* index 15 */
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bx lr
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endfunc amu_group1_set_evtype_internal
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