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refactor(cpus): convert the Cortex-A510 to use the errata framework

Browse source 
This involves replacing:
 * the reset_func with the standard cpu_reset_func_{start,end} to apply
   errata automatically
 * the <cpu>_errata_report with the errata_report_shim to report errata
   automatically
...and for each erratum:
 * the prologue with the workaround_<type>_start to do the checks and
   framework registration automatically
 * the epilogue with the workaround_<type>_end
 * the checker function with the check_erratum_<type> to make it more
   descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Note: cortex_a510.S is applicable and being used only by arm_fpga platform.

However, to test the ported changes, below steps were carried out on the
fvp and the obtained results has been verified.

Testing was conducted by:
 * Building for release with all errata flags enabled and running script
   in change 19136 to compare output of objdump for each errata.

 * Testing via script was not complete, as it directed to verify the
   check and the workaround functions of few erratas manually.

 * Manual comparison of disassembly of converted functions with non-
   converted functions

   aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
     vs
   aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

 * Manual comparison of disassembly of both both files(bl31.elf)
   ensured, the ported changes were identical and hence verified.

 * Build for release with all errata flags enabled and run default
   tftf tests.

   CROSS_COMPILE=aarch64-none-elf- \
   make PLAT=fvp \
   ARCH=aarch64 \
   DEBUG=0 \
   HW_ASSISTED_COHERENCY=1 \
   USE_COHERENT_MEM=0 \
   CTX_INCLUDE_AARCH32_REGS=0 \
   ERRATA_A510_1922240=1 \
   ERRATA_A510_2288014=1 \
   ERRATA_A510_2042739=1 \
   ERRATA_A510_2041909=1 \
   ERRATA_A510_2250311=1 \
   ERRATA_A510_2218950=1 \
   ERRATA_A510_2172148=1 \
   ERRATA_A510_2347730=1 \
   ERRATA_A510_2371937=1 \
   ERRATA_A510_2666669=1 \
   ERRATA_A510_2684597=1 \
   ERRATA_DSU_2313941=1 \
   BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
   fip all -j12

 * Build for debug with all errata enabled and step through ArmDS
   at reset to ensure that if Errata are applicable then the
   workaround functions are entered precisely.

Change-Id: Icf7aa25c0b3b30f5e2ad6db83953f7f4f0b201d9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
This commit is contained in:
Jayanth Dodderi Chidanand 2023-04-11 15:15:31 +01:00
parent 32d371d30f
commit ed6d4a3b48
2 changed files with 48 additions and 359 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

405
lib/cpus/aarch64/cortex_a510.S
View file

@ -21,50 +21,17 @@
#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
/* -------------------------------------------------- workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
* Errata Workaround for Cortex-A510 Errata #1922240.
* This applies only to revision r0p0 (fixed in r0p1)
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_1922240_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_1922240
cbz x0, 1f
/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
mrs x0, CORTEX_A510_CMPXACTLR_EL1 mrs x0, CORTEX_A510_CMPXACTLR_EL1
mov x1, #3 mov x1, #3
bfi x0, x1, #10, #2 bfi x0, x1, #10, #2
msr CORTEX_A510_CMPXACTLR_EL1, x0 msr CORTEX_A510_CMPXACTLR_EL1, x0
workaround_reset_end cortex_a510, ERRATUM(1922240)
1: check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
ret x17
endfunc errata_cortex_a510_1922240_wa
func check_errata_1922240
/* Applies to r0p0 only */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1922240
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2041909.
* This applies only to revision r0p2 and it is fixed in
* r0p3. The issue is also present in r0p0 and r0p1 but
* there is no workaround in those revisions.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x2, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2041909_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2041909
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
/* Apply workaround */ /* Apply workaround */
mov x0, xzr mov x0, xzr
msr S3_6_C15_C4_0, x0 msr S3_6_C15_C4_0, x0
@ -80,63 +47,21 @@ func errata_cortex_a510_2041909_wa
mov x0, #0x3F1 mov x0, #0x3F1
movk x0, #0x110, lsl #16 movk x0, #0x110, lsl #16
msr S3_6_C15_C4_1, x0 msr S3_6_C15_C4_1, x0
isb workaround_reset_end cortex_a510, ERRATUM(2041909)
1: check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
ret x17
endfunc errata_cortex_a510_2041909_wa
func check_errata_2041909
/* Applies only to revision r0p2 */
mov x1, #0x02
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2041909
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2042739.
* This applies only to revisions r0p0, r0p1 and r0p2.
* (fixed in r0p3)
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2042739_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2042739
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
/* Apply the workaround by disabling ReadPreferUnique. */ /* Apply the workaround by disabling ReadPreferUnique. */
mrs x0, CORTEX_A510_CPUECTLR_EL1 mrs x0, CORTEX_A510_CPUECTLR_EL1
mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
msr CORTEX_A510_CPUECTLR_EL1, x0 msr CORTEX_A510_CPUECTLR_EL1, x0
workaround_reset_end cortex_a510, ERRATUM(2042739)
1: check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
ret x17
endfunc errata_cortex_a510_2042739_wa
func check_errata_2042739
/* Applies to revisions r0p0 - r0p2 */
mov x1, #0x02
b cpu_rev_var_ls
endfunc check_errata_2042739
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2172148.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0, and is fixed in r1p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2172148_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2172148
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
/* /*
* Force L2 allocation of transient lines by setting * Force L2 allocation of transient lines by setting
* CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
@ -146,31 +71,11 @@ func errata_cortex_a510_2172148_wa
bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
msr CORTEX_A510_CPUECTLR_EL1, x0 msr CORTEX_A510_CPUECTLR_EL1, x0
workaround_reset_end cortex_a510, ERRATUM(2172148)
1: check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
ret x17
endfunc errata_cortex_a510_2172148_wa
func check_errata_2172148
/* Applies to r1p0 and lower */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2172148
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2218950.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0, and is fixed in r1p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2218950_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2218950
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
/* Source register for BFI */ /* Source register for BFI */
mov x1, #1 mov x1, #1
@ -183,37 +88,20 @@ func errata_cortex_a510_2218950_wa
mrs x0, CORTEX_A510_CMPXACTLR_EL1 mrs x0, CORTEX_A510_CMPXACTLR_EL1
bfi x0, x1, #25, #1 bfi x0, x1, #25, #1
msr CORTEX_A510_CMPXACTLR_EL1, x0 msr CORTEX_A510_CMPXACTLR_EL1, x0
workaround_reset_end cortex_a510, ERRATUM(2218950)
1: check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
ret x17
endfunc errata_cortex_a510_2218950_wa
func check_errata_2218950
/* Applies to r1p0 and lower */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2218950
/* -------------------------------------------------- /* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2250311.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0, and is fixed in r1p1.
* This workaround is not a typical errata fix. MPMM * This workaround is not a typical errata fix. MPMM
* is disabled here, but this conflicts with the BL31 * is disabled here, but this conflicts with the BL31
* MPMM support. So in addition to simply disabling * MPMM support. So in addition to simply disabling
* the feature, a flag is set in the MPMM library * the feature, a flag is set in the MPMM library
* indicating that it should not be enabled even if * indicating that it should not be enabled even if
* ENABLE_MPMM=1. * ENABLE_MPMM=1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* -------------------------------------------------- * --------------------------------------------------
*/ */
func errata_cortex_a510_2250311_wa workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2250311
cbz x0, 1f
/* Disable MPMM */ /* Disable MPMM */
mrs x0, CPUMPMMCR_EL3 mrs x0, CPUMPMMCR_EL3
bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
@ -223,61 +111,21 @@ func errata_cortex_a510_2250311_wa
/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
bl mpmm_errata_disable bl mpmm_errata_disable
#endif #endif
workaround_reset_end cortex_a510, ERRATUM(2250311)
1: check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
ret x17
endfunc errata_cortex_a510_2250311_wa
func check_errata_2250311
/* Applies to r1p0 and lower */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2250311
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2288014.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0. (fixed in r1p1)
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2288014_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2288014
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
/* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
mrs x0, CORTEX_A510_CPUACTLR_EL1 mrs x0, CORTEX_A510_CPUACTLR_EL1
mov x1, #1 mov x1, #1
bfi x0, x1, #18, #1 bfi x0, x1, #18, #1
msr CORTEX_A510_CPUACTLR_EL1, x0 msr CORTEX_A510_CPUACTLR_EL1, x0
workaround_reset_end cortex_a510, ERRATUM(2288014)
1: check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
ret x17
endfunc errata_cortex_a510_2288014_wa
func check_errata_2288014
/* Applies to r1p0 and below */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2288014
/* ----------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2347730.
* This applies to revisions r0p0 - r0p3, r1p0, r1p1.
* It is fixed in r1p2.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------
*/
func errata_cortex_a510_2347730_wa
mov x17, x30
bl check_errata_2347730
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/* /*
* Set CPUACTLR_EL1[17] to 1'b1, which disables * Set CPUACTLR_EL1[17] to 1'b1, which disables
* specific microarchitectural clock gating * specific microarchitectural clock gating
@ -286,30 +134,11 @@ func errata_cortex_a510_2347730_wa
mrs x1, CORTEX_A510_CPUACTLR_EL1 mrs x1, CORTEX_A510_CPUACTLR_EL1
orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17 orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17
msr CORTEX_A510_CPUACTLR_EL1, x1 msr CORTEX_A510_CPUACTLR_EL1, x1
1: workaround_reset_end cortex_a510, ERRATUM(2347730)
ret x17
endfunc errata_cortex_a510_2347730_wa
func check_errata_2347730 check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
/* Applies to revisions r1p1 and lower. */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2347730
/*---------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2371937.
* This applies to revisions r1p1 and lower, and is
* fixed in r1p2.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
*---------------------------------------------------
*/
func errata_cortex_a510_2371937_wa
mov x17, x30
bl check_errata_2371937
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
/* /*
* Cacheable atomic operations can be forced * Cacheable atomic operations can be forced
* to be executed near by setting * to be executed near by setting
@ -320,30 +149,11 @@ func errata_cortex_a510_2371937_wa
mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR
bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3
msr CORTEX_A510_CPUECTLR_EL1, x0 msr CORTEX_A510_CPUECTLR_EL1, x0
1: workaround_reset_end cortex_a510, ERRATUM(2371937)
ret x17
endfunc errata_cortex_a510_2371937_wa
func check_errata_2371937 check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
/* Applies to r1p1 and lower */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2371937
/* ------------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2666669
* This applies to revisions r1p1 and lower, and is fixed
* in r1p2.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* ------------------------------------------------------
*/
func errata_cortex_a510_2666669_wa
mov x17, x30
bl check_errata_2666669
cbz x0, 1f
workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
/* /*
* Workaround will set IMP_CPUACTLR_EL1[38] * Workaround will set IMP_CPUACTLR_EL1[38]
* to 0b1. * to 0b1.
@ -351,58 +161,30 @@ func errata_cortex_a510_2666669_wa
mrs x1, CORTEX_A510_CPUACTLR_EL1 mrs x1, CORTEX_A510_CPUACTLR_EL1
orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38 orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38
msr CORTEX_A510_CPUACTLR_EL1, x1 msr CORTEX_A510_CPUACTLR_EL1, x1
1: workaround_reset_end cortex_a510, ERRATUM(2666669)
ret x17
endfunc errata_cortex_a510_2666669_wa
func check_errata_2666669 check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
/* Applies to r1p1 and lower */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2666669
/* ------------------------------------------------------
* Errata Workaround for Cortex-A510 Erratum 2684597.
* This erratum applies to revision r0p0, r0p1, r0p2,
* r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
* is fixed in r1p3.
* Shall clobber: x0-x17
* ------------------------------------------------------
*/
.globl errata_cortex_a510_2684597_wa
func errata_cortex_a510_2684597_wa
mov x17, x30
/* Ensure this errata is only applied to Cortex-A510 cores */
jump_if_cpu_midr CORTEX_A510_MIDR, 1f
b 2f
1:
/* Check workaround compatibility. */
mov x0, x18
bl check_errata_2684597
cbz x0, 2f
.global erratum_cortex_a510_2684597_wa
workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
/* /*
* Many assemblers do not yet understand the "tsb csync" mnemonic, * Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction. * so use the equivalent hint instruction.
*/ */
hint #18 /* tsb csync */ hint #18 /* tsb csync */
2: workaround_runtime_end cortex_a510, ERRATUM(2684597)
ret x17
endfunc errata_cortex_a510_2684597_wa check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
/* ------------------------------------------------------
* Errata Workaround for Cortex-A510 Erratum 2684597. /*
* This erratum applies to revision r0p0, r0p1, r0p2, * ERRATA_DSU_2313941 :
* r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and * The errata is defined in dsu_helpers.S but applies to cortex_a510
* is fixed in r1p3. * as well. Henceforth creating symbolic names to the already existing errata
* Shall clobber: x0-x17 * workaround functions to get them registered under the Errata Framework.
* ------------------------------------------------------
*/ */
func check_errata_2684597 .equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
/* Applies to revision < r1p3 */ .equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
mov x1, #0x12 add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
b cpu_rev_var_ls
endfunc check_errata_2684597
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -420,105 +202,12 @@ func cortex_a510_core_pwr_dwn
ret ret
endfunc cortex_a510_core_pwr_dwn endfunc cortex_a510_core_pwr_dwn
/* errata_report_shim cortex_a510
* Errata printing function for Cortex-A510. Must follow AAPCS.
*/
#if REPORT_ERRATA
func cortex_a510_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A510_1922240, cortex_a510, 1922240
report_errata ERRATA_A510_2041909, cortex_a510, 2041909
report_errata ERRATA_A510_2042739, cortex_a510, 2042739
report_errata ERRATA_A510_2172148, cortex_a510, 2172148
report_errata ERRATA_A510_2218950, cortex_a510, 2218950
report_errata ERRATA_A510_2250311, cortex_a510, 2250311
report_errata ERRATA_A510_2288014, cortex_a510, 2288014
report_errata ERRATA_A510_2347730, cortex_a510, 2347730
report_errata ERRATA_A510_2371937, cortex_a510, 2371937
report_errata ERRATA_A510_2666669, cortex_a510, 2666669
report_errata ERRATA_A510_2684597, cortex_a510, 2684597
report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
ldp x8, x30, [sp], #16
ret
endfunc cortex_a510_errata_report
#endif
func cortex_a510_reset_func
mov x19, x30
cpu_reset_func_start cortex_a510
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
cpu_reset_func_end cortex_a510
/* Get the CPU revision and stash it in x18. */
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_DSU_2313941
bl errata_dsu_2313941_wa
#endif
#if ERRATA_A510_1922240
mov x0, x18
bl errata_cortex_a510_1922240_wa
#endif
#if ERRATA_A510_2288014
mov x0, x18
bl errata_cortex_a510_2288014_wa
#endif
#if ERRATA_A510_2042739
mov x0, x18
bl errata_cortex_a510_2042739_wa
#endif
#if ERRATA_A510_2041909
mov x0, x18
bl errata_cortex_a510_2041909_wa
#endif
#if ERRATA_A510_2250311
mov x0, x18
bl errata_cortex_a510_2250311_wa
#endif
#if ERRATA_A510_2218950
mov x0, x18
bl errata_cortex_a510_2218950_wa
#endif
#if ERRATA_A510_2371937
mov x0, x18
bl errata_cortex_a510_2371937_wa
#endif
#if ERRATA_A510_2172148
mov x0, x18
bl errata_cortex_a510_2172148_wa
#endif
#if ERRATA_A510_2347730
mov x0, x18
bl errata_cortex_a510_2347730_wa
#endif
#if ERRATA_A510_2666669
mov x0, x18
bl errata_cortex_a510_2666669_wa
#endif
isb
ret x19
endfunc cortex_a510_reset_func
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex-A510 specific * This function provides Cortex-A510 specific

2
lib/psci/aarch64/runtime_errata.S
View file

@ -20,7 +20,7 @@ func apply_cpu_pwr_dwn_errata
mov x18, x0 mov x18, x0
#if ERRATA_A510_2684597 #if ERRATA_A510_2684597
bl errata_cortex_a510_2684597_wa bl erratum_cortex_a510_2684597_wa
#endif #endif
ret x19 ret x19