From ece6fd2dac7da28a3e5d0911ec0957af6b21a70f Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 31 Jan 2019 15:01:32 +0100 Subject: [PATCH] Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSET PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base address, it is an absolute address. Rename it to avoid any confusion. Change-Id: I1f7f5e8553cb267786afe7e5f3cd4d665b610d3f Signed-off-by: Sandrine Bailleux --- include/plat/arm/css/common/css_def.h | 2 +- plat/arm/board/fvp/include/platform_def.h | 2 +- plat/arm/common/aarch32/arm_bl2_mem_params_desc.c | 4 ++-- plat/arm/common/aarch64/arm_bl2_mem_params_desc.c | 4 ++-- plat/arm/common/arm_common.c | 2 +- plat/arm/common/arm_nor_psci_mem_protect.c | 2 +- plat/xilinx/zynqmp/include/platform_def.h | 4 ++-- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 575db04f4..ec28db075 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -183,7 +183,7 @@ #endif /* CSS_LOAD_SCP_IMAGES */ /* Load address of Non-Secure Image for CSS platform ports */ -#define PLAT_ARM_NS_IMAGE_OFFSET U(0xE0000000) +#define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) /* TZC related constants */ #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index fcf363d7c..115310175 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -53,7 +53,7 @@ /* * Load address of BL33 for this platform port */ -#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) +#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c index e23dd258b..0463bc022 100644 --- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c @@ -75,11 +75,11 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #else - .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET, + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, .image_info.image_max_size = ARM_DRAM1_SIZE, #endif /* PRELOADED_BL33_BASE */ diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c index c0f42f310..96f511375 100644 --- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c @@ -176,11 +176,11 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET, + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, .image_info.image_max_size = ARM_DRAM1_SIZE, # endif /* PRELOADED_BL33_BASE */ diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 5361d4ad1..0442945b8 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -40,7 +40,7 @@ uintptr_t plat_get_ns_image_entrypoint(void) #ifdef PRELOADED_BL33_BASE return PRELOADED_BL33_BASE; #else - return PLAT_ARM_NS_IMAGE_OFFSET; + return PLAT_ARM_NS_IMAGE_BASE; #endif } diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c index dfbd12900..3a700598d 100644 --- a/plat/arm/common/arm_nor_psci_mem_protect.c +++ b/plat/arm/common/arm_nor_psci_mem_protect.c @@ -21,7 +21,7 @@ * until the end of DRAM1. * We limit the size of DRAM2 to 1 GB to avoid big delays while booting */ -#define DRAM1_NS_IMAGE_LIMIT (PLAT_ARM_NS_IMAGE_OFFSET + (32 << TWO_MB_SHIFT)) +#define DRAM1_NS_IMAGE_LIMIT (PLAT_ARM_NS_IMAGE_BASE + (32 << TWO_MB_SHIFT)) #define DRAM1_PROTECTED_SIZE (ARM_NS_DRAM1_END+1u - DRAM1_NS_IMAGE_LIMIT) static mem_region_t arm_ram_ranges[] = { diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index fb1041137..7b062fcaa 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -66,9 +66,9 @@ * BL33 specific defines. ******************************************************************************/ #ifndef PRELOADED_BL33_BASE -# define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 +# define PLAT_ARM_NS_IMAGE_BASE 0x8000000 #else -# define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE #endif /*******************************************************************************