Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-23 21:44:15 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(st-clock): adapt order of CSS on LSE and HSE

Browse source 
Fix the activation order of the CSS to prevent a faulty halt, according
to the reference manual (RM0442 Rev 6, Chapter: 10.4.3 Clock security
system CSS) it must be done after selecting the LSE clock via the RTCSRC
field.
For the HSE clock, this can be activated even when HSEON is '0'.

Signed-off-by: Christoph Fritz <chf@fritzc.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ied01baac1ccc63dcef78bf5f9180bb8628cce2d0
This commit is contained in:
Christoph Fritz 2023-11-30 10:17:00 +01:00 • committed by Yann Gautier
parent 3201497ebb
commit eca510346d
1 changed files with 7 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
drivers/st/clk/stm32mp1_clk.c
View file

@ -64,6 +64,7 @@ struct stm32_clk_platdata {
uint32_t *clksrc; uint32_t *clksrc;
uint32_t nclkdiv; uint32_t nclkdiv;
uint32_t *clkdiv; uint32_t *clkdiv;
bool lse_css;
}; };
struct stm32_clk_priv { struct stm32_clk_priv {
@ -2072,6 +2073,7 @@ static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT;
unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
struct stm32_clk_platdata *pdata = priv->pdata;
if (binding_id == RTC) { if (binding_id == RTC) {
uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
@ -2081,6 +2083,10 @@ static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
(sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
mmio_setbits_32(address, RCC_BDCR_RTCCKEN); mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
/* Configure LSE CSS */
if (pdata->lse_css) {
mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON);
}
} }
} }
@ -2176,7 +2182,6 @@ int stm32mp1_clk_init(void)
struct stm32_pll_dt_cfg *pll_conf = pdata->pll; struct stm32_pll_dt_cfg *pll_conf = pdata->pll;
int ret; int ret;
enum stm32mp1_pll_id i; enum stm32mp1_pll_id i;
bool lse_css = false;
bool pll3_preserve = false; bool pll3_preserve = false;
bool pll4_preserve = false; bool pll4_preserve = false;
bool pll4_bootrom = false; bool pll4_bootrom = false;
@ -2209,7 +2214,7 @@ int stm32mp1_clk_init(void)
bypass = fdt_clk_read_bool(name, "st,bypass"); bypass = fdt_clk_read_bool(name, "st,bypass");
digbyp = fdt_clk_read_bool(name, "st,digbypass"); digbyp = fdt_clk_read_bool(name, "st,digbypass");
lse_css = fdt_clk_read_bool(name, "st,css"); pdata->lse_css = fdt_clk_read_bool(name, "st,css");
lsedrv = fdt_clk_read_uint32_default(name, "st,drive", lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
LSEDRV_MEDIUM_HIGH); LSEDRV_MEDIUM_HIGH);
stm32mp1_lse_enable(bypass, digbyp, lsedrv); stm32mp1_lse_enable(bypass, digbyp, lsedrv);
@ -2382,10 +2387,6 @@ int stm32mp1_clk_init(void)
} }
} }
if (lse_css) {
mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON);
}
/* Switch OFF HSI if not found in device-tree */ /* Switch OFF HSI if not found in device-tree */
if (stm32mp1_osc[_HSI] == 0U) { if (stm32mp1_osc[_HSI] == 0U) {
stm32mp1_hsi_set(false); stm32mp1_hsi_set(false);