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feat(gpt): add support for large GPT mappings
This patch adds support for large GPT mappings using Contiguous descriptors. The maximum size of supported contiguous block in MB is defined in RME_GPT_MAX_BLOCK build parameter and takes values 0, 2, 32 and 512 and by default set to 2 in make_helpers/defaults.mk. Setting RME_GPT_MAX_BLOCK value to 0 disables use of Contiguous descriptors. Function gpt_tlbi_by_pa_ll() and its declaration are removed from lib/aarch64/misc_helpers.S and include/arch/aarch64/arch_helpers.h, because the GPT library now uses tlbirpalos_xxx() functions. Change-Id: Ia9a59bde1741c5666b4ca1de9324e6dfd6f734eb Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
AlexeiFedorov
Alexei Fedorov
parent
85ea97f972
commit
ec0088bbab
9 changed files with 960 additions and 238 deletions
1
Makefile
1
Makefile
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@ -1331,6 +1331,7 @@ $(eval $(call add_defines,\
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PSCI_EXTENDED_STATE_ID \
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PSCI_OS_INIT_MODE \
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RESET_TO_BL31 \
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RME_GPT_MAX_BLOCK \
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SEPARATE_CODE_AND_RODATA \
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SEPARATE_BL2_NOLOAD_REGION \
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SEPARATE_NOBITS_REGION \
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@ -812,6 +812,11 @@ Common build options
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instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
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entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
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- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define maximum size of
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supported contiguous blocks in GPT Library. This parameter can take the
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values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious
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descriptors. Default value is 2.
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- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
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file that contains the ROT private key in PEM format or a PKCS11 URI and
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enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is
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@ -807,15 +807,6 @@ static inline void tlbirpalos_512m(uintptr_t addr)
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TLBIRPALOS(addr, TLBI_SZ_512M);
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}
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/*
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* Invalidate TLBs of GPT entries by Physical address, last level.
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*
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* @pa: the starting address for the range
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* of invalidation
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* @size: size of the range of invalidation
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*/
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void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
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/* Previously defined accessor functions with incomplete register names */
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#define read_current_el() read_CurrentEl()
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,7 +15,6 @@
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.globl zero_normalmem
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.globl zeromem
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.globl memcpy16
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.globl gpt_tlbi_by_pa_ll
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.globl disable_mmu_el1
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.globl disable_mmu_el3
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@ -594,20 +593,3 @@ func fixup_gdt_reloc
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b.lo 1b
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ret
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endfunc fixup_gdt_reloc
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/*
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* TODO: Currently only supports size of 4KB,
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* support other sizes as well.
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*/
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func gpt_tlbi_by_pa_ll
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#if ENABLE_ASSERTIONS
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cmp x1, #PAGE_SIZE_4KB
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ASM_ASSERT(eq)
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tst x0, #(PAGE_SIZE_MASK)
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ASM_ASSERT(eq)
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#endif
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lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
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sys #6, c8, c4, #7, x0 /* TLBI RPALOS, <Xt> */
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dsb sy
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ret
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endfunc gpt_tlbi_by_pa_ll
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File diff suppressed because it is too large
Load diff
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@ -1,8 +1,13 @@
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#
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# Copyright (c) 2021, Arm Limited. All rights reserved.
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# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Process RME_GPT_MAX_BLOCK value
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ifeq ($(filter 0 2 32 512, ${RME_GPT_MAX_BLOCK}),)
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$(error "Invalid value for RME_GPT_MAX_BLOCK: ${RME_GPT_MAX_BLOCK}")
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endif
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GPT_LIB_SRCS := $(addprefix lib/gpt_rme/, \
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gpt_rme.c)
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@ -9,6 +9,7 @@
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#include <arch.h>
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#include <lib/gpt_rme/gpt_rme.h>
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#include <lib/spinlock.h>
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#include <lib/utils_def.h>
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/******************************************************************************/
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@ -19,7 +20,7 @@
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#define GPT_L0_TYPE_MASK UL(0xF)
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#define GPT_L0_TYPE_SHIFT U(0)
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/* For now, we don't support contiguous descriptors, only table and block */
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/* GPT level 0 table and block descriptors */
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#define GPT_L0_TYPE_TBL_DESC UL(3)
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#define GPT_L0_TYPE_BLK_DESC UL(1)
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@ -29,29 +30,63 @@
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#define GPT_L0_BLK_DESC_GPI_MASK UL(0xF)
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#define GPT_L0_BLK_DESC_GPI_SHIFT U(4)
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/* GPT level 1 descriptor bit definitions */
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/* GPT level 1 Contiguous descriptor */
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#define GPT_L1_TYPE_CONT_DESC_MASK UL(0xF)
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#define GPT_L1_TYPE_CONT_DESC UL(1)
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/* GPT level 1 Contiguous descriptor definitions */
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#define GPT_L1_CONTIG_2MB UL(1)
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#define GPT_L1_CONTIG_32MB UL(2)
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#define GPT_L1_CONTIG_512MB UL(3)
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#define GPT_L1_CONT_DESC_GPI_SHIFT U(4)
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#define GPT_L1_CONT_DESC_GPI_MASK UL(0xF)
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#define GPT_L1_CONT_DESC_CONTIG_SHIFT U(8)
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#define GPT_L1_CONT_DESC_CONTIG_MASK UL(3)
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/* GPT level 1 Granules descriptor bit definitions */
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#define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF)
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/* L1 Contiguous descriptors templates */
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#define GPT_L1_CONT_DESC_2MB \
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(GPT_L1_TYPE_CONT_DESC | \
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(GPT_L1_CONTIG_2MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
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#define GPT_L1_CONT_DESC_32MB \
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(GPT_L1_TYPE_CONT_DESC | \
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(GPT_L1_CONTIG_32MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
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#define GPT_L1_CONT_DESC_512MB \
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(GPT_L1_TYPE_CONT_DESC | \
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(GPT_L1_CONTIG_512MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
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/* Create L1 Contiguous descriptor from GPI and template */
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#define GPT_L1_GPI_CONT_DESC(_gpi, _desc) \
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((_desc) | ((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
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/* Create L1 Contiguous descriptor from Granules descriptor and size */
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#define GPT_L1_CONT_DESC(_desc, _size) \
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(GPT_L1_CONT_DESC_##_size | \
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(((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) << \
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GPT_L1_CONT_DESC_GPI_SHIFT))
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/* Create L1 Contiguous descriptor from GPI and size */
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#define GPT_L1_CONT_DESC_SIZE(_gpi, _size) \
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(GPT_L1_CONT_DESC_##_size | \
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(((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
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#define GPT_L1_GPI_BYTE(_gpi) (uint64_t)((_gpi) | ((_gpi) << 4))
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#define GPT_L1_GPI_HALF(_gpi) (GPT_L1_GPI_BYTE(_gpi) | (GPT_L1_GPI_BYTE(_gpi) << 8))
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#define GPT_L1_GPI_WORD(_gpi) (GPT_L1_GPI_HALF(_gpi) | (GPT_L1_GPI_HALF(_gpi) << 16))
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/*
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* This macro fills out every GPI entry in a granules descriptor to the same
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* value.
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* This macro generates a Granules descriptor
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* with the same value for every GPI entry.
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*/
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#define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
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((uint64_t)(_gpi) << 4*1) | \
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((uint64_t)(_gpi) << 4*2) | \
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((uint64_t)(_gpi) << 4*3) | \
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((uint64_t)(_gpi) << 4*4) | \
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((uint64_t)(_gpi) << 4*5) | \
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((uint64_t)(_gpi) << 4*6) | \
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((uint64_t)(_gpi) << 4*7) | \
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((uint64_t)(_gpi) << 4*8) | \
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((uint64_t)(_gpi) << 4*9) | \
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((uint64_t)(_gpi) << 4*10) | \
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((uint64_t)(_gpi) << 4*11) | \
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((uint64_t)(_gpi) << 4*12) | \
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((uint64_t)(_gpi) << 4*13) | \
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((uint64_t)(_gpi) << 4*14) | \
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((uint64_t)(_gpi) << 4*15))
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#define GPT_BUILD_L1_DESC(_gpi) (GPT_L1_GPI_WORD(_gpi) | (GPT_L1_GPI_WORD(_gpi) << 32))
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#define GPT_L1_SECURE_DESC GPT_BUILD_L1_DESC(GPT_GPI_SECURE)
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#define GPT_L1_NS_DESC GPT_BUILD_L1_DESC(GPT_GPI_NS)
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#define GPT_L1_REALM_DESC GPT_BUILD_L1_DESC(GPT_GPI_REALM)
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#define GPT_L1_ANY_DESC GPT_BUILD_L1_DESC(GPT_GPI_ANY)
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/******************************************************************************/
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/* GPT platform configuration */
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@ -106,17 +141,44 @@ typedef enum {
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PGS_64KB_P = 16U
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} gpt_p_val_e;
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#define LOCK_SIZE sizeof(((bitlock_t *)NULL)->lock)
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#define LOCK_TYPE typeof(((bitlock_t *)NULL)->lock)
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#define LOCK_BITS (LOCK_SIZE * 8U)
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/*
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* Internal structure to retrieve the values from get_gpi_info();
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* Internal structure to retrieve the values from get_gpi_params();
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*/
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typedef struct gpi_info {
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typedef struct {
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uint64_t gpt_l1_desc;
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uint64_t *gpt_l1_addr;
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unsigned int idx;
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unsigned int gpi_shift;
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unsigned int gpi;
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bitlock_t *lock;
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LOCK_TYPE mask;
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} gpi_info_t;
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/*
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* Look up structure for contiguous blocks and descriptors
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*/
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typedef struct {
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size_t size;
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unsigned int desc;
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} gpt_fill_lookup_t;
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typedef void (*gpt_shatter_func)(uintptr_t base, const gpi_info_t *gpi_info,
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uint64_t l1_desc);
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typedef void (*gpt_tlbi_func)(uintptr_t base);
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/*
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* Look-up structure for
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* invalidating TLBs of GPT entries by Physical address, last level.
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*/
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typedef struct {
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gpt_tlbi_func function;
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size_t mask;
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} gpt_tlbi_lookup_t;
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/* Max valid value for PGS */
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#define GPT_PGS_MAX (2U)
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@ -136,8 +198,8 @@ typedef struct gpi_info {
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* special case we'll get a negative width value which does not make sense and
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* would cause problems.
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*/
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#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
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((_t) - GPT_S_VAL) : (0U))
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#define GPT_L0_IDX_WIDTH(_t) (((unsigned int)(_t) > GPT_S_VAL) ? \
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((unsigned int)(_t) - GPT_S_VAL) : (0U))
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/* Bit shift for the L0 index field in a PA */
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#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
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@ -173,10 +235,11 @@ typedef struct gpi_info {
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* the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ
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* (s) will result in a positive width value.
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*/
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#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
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#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - \
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((unsigned int)(_p) + 3U))
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/* Bit shift for the L1 index field */
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#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
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#define GPT_L1_IDX_SHIFT(_p) ((unsigned int)(_p) + 4U)
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/*
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* Mask for the L1 index field, must be shifted.
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@ -196,7 +259,10 @@ typedef struct gpi_info {
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#define GPT_L1_GPI_IDX_MASK (0xF)
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/* Total number of entries in each L1 table */
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#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
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#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1UL)
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/* Number of L1 entries in 2MB block */
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#define GPT_L1_ENTRY_COUNT_2MB(_p) (SZ_2M >> GPT_L1_IDX_SHIFT(_p))
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/* Total size in bytes of each L1 table */
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#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
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@ -206,10 +272,13 @@ typedef struct gpi_info {
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/******************************************************************************/
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/* Protected space actual size in bytes */
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#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
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#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (unsigned int)(_t))
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/* Granule actual size in bytes */
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#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
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#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (unsigned int)(_p))
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/* Number of granules in 2MB block */
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#define GPT_PGS_COUNT_2MB(_p) (1UL << (21U - (unsigned int)(_p)))
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/* L0 GPT region size in bytes */
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#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
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@ -221,7 +290,8 @@ typedef struct gpi_info {
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* This definition is used to determine if a physical address lies on an L0
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* region boundary.
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*/
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#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
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#define GPT_IS_L0_ALIGNED(_pa) \
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(((_pa) & (GPT_L0_REGION_SIZE - UL(1))) == UL(0))
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/* Get the type field from an L0 descriptor */
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#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
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@ -246,16 +316,43 @@ typedef struct gpi_info {
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(GPT_L0_TBL_DESC_L1ADDR_MASK << \
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GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
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/* Get the GPI from L1 Contiguous descriptor */
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#define GPT_L1_CONT_GPI(_desc) \
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(((_desc) >> GPT_L1_CONT_DESC_GPI_SHIFT) & GPT_L1_CONT_DESC_GPI_MASK)
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/* Get the GPI from L1 Granules descriptor */
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#define GPT_L1_GRAN_GPI(_desc) ((_desc) & GPT_L1_GRAN_DESC_GPI_MASK)
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/* Get the Contig from L1 Contiguous descriptor */
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#define GPT_L1_CONT_CONTIG(_desc) \
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(((_desc) >> GPT_L1_CONT_DESC_CONTIG_SHIFT) & \
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GPT_L1_CONT_DESC_CONTIG_MASK)
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/* Get the index into the L1 table from a physical address */
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#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
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GPT_L1_IDX_MASK(_p))
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#define GPT_L1_IDX(_p, _pa) \
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(((_pa) >> GPT_L1_IDX_SHIFT(_p)) & GPT_L1_IDX_MASK(_p))
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/* Get the index of the GPI within an L1 table entry from a physical address */
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#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
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GPT_L1_GPI_IDX_MASK)
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#define GPT_L1_GPI_IDX(_p, _pa) \
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(((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & GPT_L1_GPI_IDX_MASK)
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/* Determine if an address is granule-aligned */
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#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
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== U(0))
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#define GPT_IS_L1_ALIGNED(_p, _pa) \
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(((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - UL(1))) == UL(0))
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/* Get aligned addresses */
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#define ALIGN_2MB(_addr) ((_addr) & ~(SZ_2M - 1UL))
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#define ALIGN_32MB(_addr) ((_addr) & ~(SZ_32M - 1UL))
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#define ALIGN_512MB(_addr) ((_addr) & ~(SZ_512M - 1UL))
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/* Determine if region is contiguous */
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#define GPT_REGION_IS_CONT(_len, _addr, _size) \
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(((_len) >= (_size)) && (((_addr) & ((_size) - UL(1))) == UL(0)))
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/* Get 32MB block number in 512MB block: 0-15 */
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#define GET_32MB_NUM(_addr) ((_addr >> 25) & 0xF)
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/* Get 2MB block number in 32MB block: 0-15 */
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#define GET_2MB_NUM(_addr) ((_addr >> 21) & 0xF)
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#endif /* GPT_RME_PRIVATE_H */
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@ -139,6 +139,9 @@ FW_ENC_STATUS := 0
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# For Chain of Trust
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GENERATE_COT := 0
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# Default maximum size of GPT contiguous block
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RME_GPT_MAX_BLOCK := 2
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# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
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# default, they are for Secure EL1.
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GICV2_G0_FOR_EL3 := 0
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ FVP_GICR_REGION_PROTECTION := 0
|
|||
|
||||
FVP_DT_PREFIX := fvp-base-gicv3-psci
|
||||
|
||||
# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
|
||||
# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
|
||||
# the FVP platform. This option defaults to 256.
|
||||
FVP_TRUSTED_SRAM_SIZE := 256
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue