From ebc090fbf47a25a1ef84657d03198fc3a29d28e3 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Sun, 2 Jun 2024 22:59:09 -0500 Subject: [PATCH] fix(cpus): workaround for CVE-2024-5660 for Cortex-X925 Implements mitigation for CVE-2024-5660 that affects Cortex-X925 revisions r0p0, r0p1. The workaround is to disable the hardware page aggregation at EL3 by setting CPUECTLR_EL1[46] = 1'b1. Public Documentation: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660 Change-Id: I9d5a07ca6b89b27d8876f4349eff2af26c962d8a Signed-off-by: Sona Mathew --- lib/cpus/aarch64/cortex_x925.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 8109ffba2..3a316649a 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -21,6 +21,13 @@ #error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ +workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 + sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) +workaround_reset_end cortex_x925, CVE(2024, 5660) + +check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) + cpu_reset_func_start cortex_x925 /* Disable speculative loads */ msr SSBS, xzr