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fix(cpus): workaround for Cortex-X3 erratum 2266875

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Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to
invalidate all branch predictor resources regardless of context.

SDEN Documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
(cherry picked from commit a65c5ba351)
This commit is contained in:
Bipin Ravi 2023-12-20 14:53:37 -06:00 • committed by Yann Gautier
parent 70bd2640b9
commit eadc24b6b1
5 changed files with 28 additions and 8 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -771,6 +771,10 @@ For Cortex-X3, the following errata build flags are defined :
CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
the CPU and is still open. the CPU and is still open.
- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3
CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
is fixed in r1p1.
- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 - ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
fixed in r1p2. fixed in r1p2.

7
include/lib/cpus/aarch64/cortex_x3.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved. * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -25,6 +25,11 @@
#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) #define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0
/******************************************************************************* /*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions. * CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/ ******************************************************************************/

6
lib/cpus/aarch64/cortex_x3.S
View file

@ -33,6 +33,12 @@ workaround_reset_end cortex_x3, ERRATUM(2070301)
check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
workaround_reset_end cortex_x3, ERRATUM(2266875)
check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0)
workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB

4
lib/cpus/cpu-ops.mk
View file

@ -779,6 +779,10 @@ CPU_FLAG_LIST += ERRATA_X2_2778471
# still open. # still open.
CPU_FLAG_LIST += ERRATA_X3_2070301 CPU_FLAG_LIST += ERRATA_X3_2070301
# Flag to apply erratum 2266875 workaround during reset. This erratum applies
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_X3_2266875
# Flag to apply erratum 2302506 workaround during reset. This erratum applies # Flag to apply erratum 2302506 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2302506 CPU_FLAG_LIST += ERRATA_X3_2302506

15
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -446,13 +446,14 @@ struct em_cpu_list cpu_list[] = {
.cpu_partnumber = CORTEX_X3_MIDR, .cpu_partnumber = CORTEX_X3_MIDR,
.cpu_errata_list = { .cpu_errata_list = {
[0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301}, [0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301},
[1] = {2302506, 0x00, 0x11, ERRATA_X3_2302506}, [1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875},
[2] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, [2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
[3] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, [3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[4] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, [4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
[5] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, [5] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
[6] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, [6] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
[7 ... ERRATA_LIST_END] = UNDEF_ERRATA, [7] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
[8 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* CORTEX_X3_H_INC */ #endif /* CORTEX_X3_H_INC */