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Merge pull request #1723 from soby-mathew/sm/reset_bl31_fix
FVP: Fixes for RESET_TO_BL31
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
ea9c332d12
3 changed files with 59 additions and 41 deletions
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@ -66,11 +66,11 @@ SECTIONS
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__CPU_OPS_END__ = .;
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/*
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* Keep the .got section in the RO section as the it is patched
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* Keep the .got section in the RO section as it is patched
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* prior to enabling the MMU and having the .got in RO is better for
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* security.
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* security. GOT is a table of addresses so ensure 8-byte alignment.
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*/
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. = ALIGN(16);
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. = ALIGN(8);
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__GOT_START__ = .;
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*(.got)
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__GOT_END__ = .;
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@ -112,6 +112,16 @@ SECTIONS
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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/*
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* Keep the .got section in the RO section as it is patched
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* prior to enabling the MMU and having the .got in RO is better for
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* security. GOT is a table of addresses so ensure 8-byte alignment.
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*/
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. = ALIGN(8);
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__GOT_START__ = .;
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*(.got)
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__GOT_END__ = .;
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/* Place pubsub sections for events */
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. = ALIGN(8);
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#include <pubsub_events.h>
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@ -165,11 +175,12 @@ SECTIONS
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__DATA_END__ = .;
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} >RAM
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. = ALIGN(16);
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/*
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* .rela.dyn needs to come after .data for the read-elf utility to parse
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* this section correctly.
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* this section correctly. Ensure 8-byte alignment so that the fields of
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* RELA data structure are aligned.
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*/
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. = ALIGN(8);
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__RELA_START__ = .;
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.rela.dyn . : {
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} >RAM
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@ -1875,16 +1875,16 @@ with 8 CPUs using the AArch64 build of TF-A.
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBAR=0x04020000 \
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-C cluster0.cpu1.RVBAR=0x04020000 \
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-C cluster0.cpu2.RVBAR=0x04020000 \
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-C cluster0.cpu3.RVBAR=0x04020000 \
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-C cluster1.cpu0.RVBAR=0x04020000 \
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-C cluster1.cpu1.RVBAR=0x04020000 \
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-C cluster1.cpu2.RVBAR=0x04020000 \
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-C cluster1.cpu3.RVBAR=0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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-C cluster0.cpu0.RVBAR=0x04010000 \
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-C cluster0.cpu1.RVBAR=0x04010000 \
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-C cluster0.cpu2.RVBAR=0x04010000 \
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-C cluster0.cpu3.RVBAR=0x04010000 \
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-C cluster1.cpu0.RVBAR=0x04010000 \
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-C cluster1.cpu1.RVBAR=0x04010000 \
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-C cluster1.cpu2.RVBAR=0x04010000 \
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-C cluster1.cpu3.RVBAR=0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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@ -1892,6 +1892,9 @@ with 8 CPUs using the AArch64 build of TF-A.
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Notes:
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- Since Position Independent Executable (PIE) support is enabled for BL31
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in this config, it can be loaded at any valid address for execution.
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- Since a FIP is not loaded when using BL31 as reset entrypoint, the
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``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
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parameter is needed to load the individual bootloader images in memory.
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@ -1932,14 +1935,14 @@ with 8 CPUs using the AArch32 build of TF-A.
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-C cluster1.cpu1.CONFIG64=0 \
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-C cluster1.cpu2.CONFIG64=0 \
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-C cluster1.cpu3.CONFIG64=0 \
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-C cluster0.cpu0.RVBAR=0x04001000 \
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-C cluster0.cpu1.RVBAR=0x04001000 \
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-C cluster0.cpu2.RVBAR=0x04001000 \
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-C cluster0.cpu3.RVBAR=0x04001000 \
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-C cluster1.cpu0.RVBAR=0x04001000 \
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-C cluster1.cpu1.RVBAR=0x04001000 \
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-C cluster1.cpu2.RVBAR=0x04001000 \
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-C cluster1.cpu3.RVBAR=0x04001000 \
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-C cluster0.cpu0.RVBAR=0x04002000 \
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-C cluster0.cpu1.RVBAR=0x04002000 \
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-C cluster0.cpu2.RVBAR=0x04002000 \
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-C cluster0.cpu3.RVBAR=0x04002000 \
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-C cluster1.cpu0.RVBAR=0x04002000 \
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-C cluster1.cpu1.RVBAR=0x04002000 \
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-C cluster1.cpu2.RVBAR=0x04002000 \
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-C cluster1.cpu3.RVBAR=0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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@ -1962,16 +1965,16 @@ boot Linux with 8 CPUs using the AArch64 build of TF-A.
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBARADDR=0x04020000 \
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-C cluster0.cpu1.RVBARADDR=0x04020000 \
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-C cluster0.cpu2.RVBARADDR=0x04020000 \
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-C cluster0.cpu3.RVBARADDR=0x04020000 \
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-C cluster1.cpu0.RVBARADDR=0x04020000 \
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-C cluster1.cpu1.RVBARADDR=0x04020000 \
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-C cluster1.cpu2.RVBARADDR=0x04020000 \
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-C cluster1.cpu3.RVBARADDR=0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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-C cluster0.cpu0.RVBARADDR=0x04010000 \
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-C cluster0.cpu1.RVBARADDR=0x04010000 \
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-C cluster0.cpu2.RVBARADDR=0x04010000 \
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-C cluster0.cpu3.RVBARADDR=0x04010000 \
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-C cluster1.cpu0.RVBARADDR=0x04010000 \
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-C cluster1.cpu1.RVBARADDR=0x04010000 \
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-C cluster1.cpu2.RVBARADDR=0x04010000 \
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-C cluster1.cpu3.RVBARADDR=0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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@ -1990,10 +1993,10 @@ boot Linux with 4 CPUs using the AArch32 build of TF-A.
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBARADDR=0x04001000 \
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-C cluster0.cpu1.RVBARADDR=0x04001000 \
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-C cluster0.cpu2.RVBARADDR=0x04001000 \
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-C cluster0.cpu3.RVBARADDR=0x04001000 \
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-C cluster0.cpu0.RVBARADDR=0x04002000 \
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-C cluster0.cpu1.RVBARADDR=0x04002000 \
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-C cluster0.cpu2.RVBARADDR=0x04002000 \
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-C cluster0.cpu3.RVBARADDR=0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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@ -407,12 +407,16 @@
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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#elif (RESET_TO_BL31)
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/* Ensure Position Independent support (PIE) is enabled for this config.*/
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# if !ENABLE_PIE
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# error "BL31 must be a PIE if RESET_TO_BL31=1."
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# endif
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/*
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* Put BL31_BASE in the middle of the Trusted SRAM.
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* Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
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* used for building BL31 when RESET_TO_BL31=1.
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*/
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#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#define BL31_BASE 0x0
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#define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
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#else
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/* Put BL31 below BL2 in the Trusted SRAM.*/
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#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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