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feat(imx8ulp): allow RTD to reset APD through MU

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Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174
This commit is contained in:
Ye Li 2022-11-21 17:54:11 +08:00 • committed by Jacky Bai
parent ab787dba77
commit ea1f7a2e10
3 changed files with 6 additions and 0 deletions
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2
plat/imx/imx8ulp/apd_context.c
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@ -561,6 +561,8 @@ void imx_apd_ctx_restore(unsigned int proc_num)
/* FIXME: make uart work for ATF */
mmio_write_32(IMX_LPUART_BASE + 0x18, 0xc0000);
/* Allow M core to reset A core */
mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2));
/*
* Ask S400 to release caam to APD as it is owned by s400
*/

3
plat/imx/imx8ulp/imx8ulp_bl31_setup.c
View file

@ -103,6 +103,9 @@ void bl31_plat_arch_setup(void)
/* TODO: Hack, refine this piece, scmi channel free */
mmio_write_32(SRAM0_BASE + 0x4, 1);
/* Allow M core to reset A core */
mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2));
}
void bl31_platform_setup(void)

1
plat/imx/imx8ulp/include/platform_def.h
View file

@ -65,6 +65,7 @@
#define IMX_SIM2_BASE U(0x2da50000)
#define IMX_CGC2_BASE U(0x2da60000)
#define IMX_PCC5_BASE U(0x2da70000)
#define IMX_MU0B_BASE U(0x29220000)
#define IMX_CMC1_BASE U(0x29240000)
#define IMX_WUU1_BASE U(0x29260000)
#define IMX_SIM1_BASE U(0x29290000)