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fix(rcar3): change RAM protection configurations

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Change RAM protection control not to overwrite the images by DSMAC.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I038dc2bf90e721692d392ea4de5441647aa62029
---
Marek: - Move axi DRAM out and merge AXI_SPTCR15 setting into it
       - Set AXI_SPTCR1 from 0x0E000E0EU to 0x0E000000U to let
         TEE pick TFA DT
This commit is contained in:
Toshiyuki Ogasahara 2021-07-12 18:39:52 +09:00 • committed by Marek Vasut
parent 4f7e0fa38f
commit e9afde1a2e
2 changed files with 66 additions and 42 deletions
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102
plat/renesas/common/bl2_secure_setting.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -107,8 +107,10 @@ static const struct {
/* /*
* Security group 0 attribute setting for master ports 3 * Security group 0 attribute setting for master ports 3
* Security group 1 attribute setting for master ports 3 * Security group 1 attribute setting for master ports 3
* {SEC_GRP0CR3, 0x00000000U}, */
* {SEC_GRP1CR3, 0x00000000U}, { SEC_GRP0CR3, 0x00003780U },
{ SEC_GRP1CR3, 0x00003780U },
/*
* Security group 0 attribute setting for slave ports 0 * Security group 0 attribute setting for slave ports 0
* Security group 1 attribute setting for slave ports 0 * Security group 1 attribute setting for slave ports 0
* {SEC_GRP0COND0, 0x00000000U}, * {SEC_GRP0COND0, 0x00000000U},
@ -259,46 +261,12 @@ static const struct {
}; };
/* AXI settings */ /* AXI settings */
static const struct { struct axi_t {
uint32_t reg; uint32_t reg;
uint32_t val; uint32_t val;
} axi[] = { };
/*
* DRAM protection static const struct axi_t axi[] = {
* AXI dram protected area division
*/
{AXI_DPTDIVCR0, 0x0E0403F0U},
{AXI_DPTDIVCR1, 0x0E0407E0U},
{AXI_DPTDIVCR2, 0x0E080000U},
{AXI_DPTDIVCR3, 0x0E080000U},
{AXI_DPTDIVCR4, 0x0E080000U},
{AXI_DPTDIVCR5, 0x0E080000U},
{AXI_DPTDIVCR6, 0x0E080000U},
{AXI_DPTDIVCR7, 0x0E080000U},
{AXI_DPTDIVCR8, 0x0E080000U},
{AXI_DPTDIVCR9, 0x0E080000U},
{AXI_DPTDIVCR10, 0x0E080000U},
{AXI_DPTDIVCR11, 0x0E080000U},
{AXI_DPTDIVCR12, 0x0E080000U},
{AXI_DPTDIVCR13, 0x0E080000U},
{AXI_DPTDIVCR14, 0x0E080000U},
/* AXI dram protected area setting */
{AXI_DPTCR0, 0x0E000000U},
{AXI_DPTCR1, 0x0E000E0EU},
{AXI_DPTCR2, 0x0E000000U},
{AXI_DPTCR3, 0x0E000000U},
{AXI_DPTCR4, 0x0E000000U},
{AXI_DPTCR5, 0x0E000000U},
{AXI_DPTCR6, 0x0E000000U},
{AXI_DPTCR7, 0x0E000000U},
{AXI_DPTCR8, 0x0E000000U},
{AXI_DPTCR9, 0x0E000000U},
{AXI_DPTCR10, 0x0E000000U},
{AXI_DPTCR11, 0x0E000000U},
{AXI_DPTCR12, 0x0E000000U},
{AXI_DPTCR13, 0x0E000000U},
{AXI_DPTCR14, 0x0E000000U},
{AXI_DPTCR15, 0x0E000000U},
/* /*
* SRAM ptotection * SRAM ptotection
* AXI sram protected area division * AXI sram protected area division
@ -337,6 +305,47 @@ static const struct {
{AXI_SPTCR15, 0x0E000000U} {AXI_SPTCR15, 0x0E000000U}
}; };
static const struct axi_t axi_dram[] = {
/*
* DRAM protection
* AXI dram protected area division
*/
{AXI_DPTDIVCR0, 0x0E0403F0U},
{AXI_DPTDIVCR1, 0x0E0407E0U},
{AXI_DPTDIVCR2, 0x0E080000U},
{AXI_DPTDIVCR3, 0x0E080000U},
{AXI_DPTDIVCR4, 0x0E080000U},
{AXI_DPTDIVCR5, 0x0E080000U},
{AXI_DPTDIVCR6, 0x0E080000U},
{AXI_DPTDIVCR7, 0x0E080000U},
{AXI_DPTDIVCR8, 0x0E080000U},
{AXI_DPTDIVCR9, 0x0E080000U},
{AXI_DPTDIVCR10, 0x0E080000U},
{AXI_DPTDIVCR11, 0x0E080000U},
{AXI_DPTDIVCR12, 0x0E080000U},
{AXI_DPTDIVCR13, 0x0E080000U},
{AXI_DPTDIVCR14, 0x0E080000U},
/* AXI dram protected area setting */
{AXI_DPTCR0, 0x0E000000U},
{AXI_DPTCR1, 0x0E000E0EU},
{AXI_DPTCR2, 0x0E000000U},
{AXI_DPTCR3, 0x0E000000U},
{AXI_DPTCR4, 0x0E000000U},
{AXI_DPTCR5, 0x0E000000U},
{AXI_DPTCR6, 0x0E000000U},
{AXI_DPTCR7, 0x0E000000U},
{AXI_DPTCR8, 0x0E000000U},
{AXI_DPTCR9, 0x0E000000U},
{AXI_DPTCR10, 0x0E000000U},
{AXI_DPTCR11, 0x0E000000U},
{AXI_DPTCR12, 0x0E000000U},
{AXI_DPTCR13, 0x0E000000U},
{AXI_DPTCR14, 0x0E000000U},
{AXI_DPTCR15, 0x0E000000U},
/* AXI sram protected area setting */
{AXI_SPTCR15, 0x0E000000U}
};
static void lifec_security_setting(void) static void lifec_security_setting(void)
{ {
uint32_t i; uint32_t i;
@ -345,7 +354,7 @@ static void lifec_security_setting(void)
mmio_write_32(lifec[i].reg, lifec[i].val); mmio_write_32(lifec[i].reg, lifec[i].val);
} }
/* SRAM/DRAM protection setting */ /* SRAM protection setting */
static void axi_security_setting(void) static void axi_security_setting(void)
{ {
uint32_t i; uint32_t i;
@ -354,6 +363,15 @@ static void axi_security_setting(void)
mmio_write_32(axi[i].reg, axi[i].val); mmio_write_32(axi[i].reg, axi[i].val);
} }
/* DRAM protection setting */
void bl2_ram_security_setting_finish(void)
{
uint32_t i;
for (i = 0; i < ARRAY_SIZE(axi_dram); i++)
mmio_write_32(axi_dram[i].reg, axi_dram[i].val);
}
void bl2_secure_setting(void) void bl2_secure_setting(void)
{ {
lifec_security_setting(); lifec_security_setting();

6
plat/renesas/rcar/bl2_plat_setup.c
View file

@ -68,6 +68,7 @@ extern void plat_rcar_gic_init(void);
extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
extern void bl2_system_cpg_init(void); extern void bl2_system_cpg_init(void);
extern void bl2_secure_setting(void); extern void bl2_secure_setting(void);
extern void bl2_ram_security_setting_finish(void);
extern void bl2_cpg_init(void); extern void bl2_cpg_init(void);
extern void rcar_io_emmc_setup(void); extern void rcar_io_emmc_setup(void);
extern void rcar_io_setup(void); extern void rcar_io_setup(void);
@ -1285,6 +1286,11 @@ void bl2_el3_plat_arch_setup(void)
#endif #endif
} }
void bl2_el3_plat_prepare_exit(void)
{
bl2_ram_security_setting_finish();
}
void bl2_platform_setup(void) void bl2_platform_setup(void)
{ {