Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-25 14:25:44 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

refactor(cpus): convert Rainier to use errata framework

Browse source 
This involves replacing:
 * the reset_func with the standard cpu_reset_func_{start,end} to apply
   errata automatically
 * the <cpu>_errata_report with the errata_report_shim to report errata
   automatically
as well as specifically related to single errata for this CPU:
 * the prologue with the workaround_<type>_start to do the checks and
   framework registration automatically
 * the epilogue with the workaround_<type>_end
 * the checker function with the check_erratum_<type> to make it more
   descriptive

Change-Id: I31cacbbdd4caa12b32e2c65ec456b0ab6b1a9101
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
This commit is contained in:
Maksims Svecovs 2023-04-19 16:48:05 +01:00
parent e5cc52dbf6
commit e8b30c2921
1 changed files with 13 additions and 82 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

95
lib/cpus/aarch64/rainier.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, Arm Limited. All rights reserved. * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -41,78 +41,30 @@ func rainier_disable_speculative_loads
ret ret
endfunc rainier_disable_speculative_loads endfunc rainier_disable_speculative_loads
/* -------------------------------------------------- /* Rainier R0P0 is based on Neoverse N1 R4P0. */
* Errata Workaround for Neoverse N1 Errata #1868343. workaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343
* This applies to revision <= r4p0 of Neoverse N1. sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13
* This workaround is the same as the workaround for workaround_reset_end rainier, ERRATUM(1868343)
* errata 1262606 and 1275112 but applies to a wider
* revision range.
* Rainier R0P0 is based on Neoverse N1 R4P0 so the
* workaround checks for r0p0 version of Rainier CPU.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1 & x17
* --------------------------------------------------
*/
func errata_n1_1868343_wa
/*
* Compare x0 against revision r4p0
*/
mov x17, x30
bl check_errata_1868343
cbz x0, 1f
mrs x1, RAINIER_CPUACTLR_EL1
orr x1, x1, RAINIER_CPUACTLR_EL1_BIT_13
msr RAINIER_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_n1_1868343_wa
func check_errata_1868343 check_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0)
/* Applies to r0p0 of Rainier CPU */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1868343
func rainier_reset_func
mov x19, x30
cpu_reset_func_start rainier
bl rainier_disable_speculative_loads bl rainier_disable_speculative_loads
/* Forces all cacheable atomic instructions to be near */ /* Forces all cacheable atomic instructions to be near */
mrs x0, RAINIER_CPUACTLR2_EL1 sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2
orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
msr RAINIER_CPUACTLR2_EL1, x0
isb
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_N1_1868343
mov x0, x18
bl errata_n1_1868343_wa
#endif
#if ENABLE_FEAT_AMU #if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3 sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT
orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
msr actlr_el3, x0
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */ /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2 sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT
orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
msr actlr_el2, x0
/* Enable group0 counters */ /* Enable group0 counters */
mov x0, #RAINIER_AMU_GROUP0_MASK mov x0, #RAINIER_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0 msr CPUAMCNTENSET_EL0, x0
#endif #endif
cpu_reset_func_end rainier
isb
ret x19
endfunc rainier_reset_func
/* --------------------------------------------- /* ---------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -123,33 +75,12 @@ func rainier_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, RAINIER_CPUPWRCTLR_EL1 sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK
orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
msr RAINIER_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc rainier_core_pwr_dwn endfunc rainier_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim rainier
/*
* Errata printing function for Rainier. Must follow AAPCS.
*/
func rainier_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_N1_1868343, rainier, 1868343
ldp x8, x30, [sp], #16
ret
endfunc rainier_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Rainier specific * This function provides Rainier specific