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refactor(tc): move the FVP RoS to a separate file

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In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to the FPGA's, to reduce the number of ifdefs and make FVP-only changes
easier.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib7999d3e39de55ab4a30e68dd81f95120be15a8c
This commit is contained in:
Boyan Karatotev 2023-11-14 09:38:08 +00:00
parent 1b8ed0993f
commit e862f0bf0a
2 changed files with 41 additions and 30 deletions
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33
fdts/tc.dts
View file

@ -10,6 +10,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "platform_def.h"
#include "tc_vers.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc_fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
/ {
compatible = "arm,tc";
@ -462,14 +465,6 @@
status = "okay";
};
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};
vencoder {
compatible = "drm,virtual-encoder";
port {
@ -497,22 +492,6 @@
smsc,irq-push-pull;
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
bp_clock24mhz: clock24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -520,12 +499,6 @@
clock-output-names = "bp:clock24mhz";
};
virtio_block@1c130000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
/* spec lists this wrong */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";

38
fdts/tc_fvp.dtsi Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/ {
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
virtio_block@1c130000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
/* spec lists this wrong */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
};