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https://github.com/ARM-software/arm-trusted-firmware.git
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Tegra: Support for Tegra's T132 platforms
This patch implements support for T132 (Denver CPU) based Tegra platforms. The following features have been added: * SiP calls to switch T132 CPU's AARCH mode * Complete PSCI support, including 'System Suspend' * Platform specific MMIO settings * Locking of CPU vector registers Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
3a8c55f600
commit
e7d4caa298
7 changed files with 493 additions and 5 deletions
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@ -1,5 +1,8 @@
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Tegra-T210 Overview
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====================
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Tegra SoCs - Overview
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======================
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* T210
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-------
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T210 has Quad ARM® Cortex®-A57 cores in a switched configuration with a
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companion set of quad ARM Cortex-A53 cores. The Cortex-A57 and A53 cores
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@ -9,6 +12,34 @@ including legacy ARMv7 applications. The Cortex-A57 processors each have
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Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
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and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
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* T132
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-------
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Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
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fully ARMv8 architecture compatible. Each of the two Denver cores
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implements a 7-way superscalar microarchitecture (up to 7 concurrent
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micro-ops can be executed per clock), and includes a 128KB 4-way L1
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instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
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cache, which services both cores.
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Denver implements an innovative process called Dynamic Code Optimization,
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which optimizes frequently used software routines at runtime into dense,
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highly tuned microcode-equivalent routines. These are stored in a
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dedicated, 128MB main-memory-based optimization cache. After being read
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into the instruction cache, the optimized micro-ops are executed,
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re-fetched and executed from the instruction cache as long as needed and
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capacity allows.
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Effectively, this reduces the need to re-optimize the software routines.
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Instead of using hardware to extract the instruction-level parallelism
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(ILP) inherent in the code, Denver extracts the ILP once via software
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techniques, and then executes those routines repeatedly, thus amortizing
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the cost of ILP extraction over the many execution instances.
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Denver also features new low latency power-state transitions, in addition
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to extensive power-gating and dynamic voltage and clock scaling based on
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workloads.
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Directory structure
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====================
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@ -25,9 +56,9 @@ without changing any makefiles.
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Preparing the BL31 image to run on Tegra SoCs
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===================================================
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CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
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TARGET_SOC=<target-soc e.g. t210> BL32=<path-to-trusted-os-binary> \
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SPD=<dispatcher e.g. tlkd> all
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'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
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TARGET_SOC=<target-soc e.g. t210|t132> BL32=<path-to-trusted-os-binary> \
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SPD=<dispatcher e.g. tlkd> all'
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Power Management
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================
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@ -28,6 +28,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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@ -38,7 +39,21 @@
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#include <runtime_svc.h>
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#include <tegra_private.h>
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#define NS_SWITCH_AARCH32 1
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#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
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/*******************************************************************************
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* Tegra SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_AARCH_SWITCH 0x82000004
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/*******************************************************************************
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* SPSR settings for AARCH32/AARCH64 modes
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******************************************************************************/
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#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
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DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
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#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
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/*******************************************************************************
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* This function is responsible for handling all SiP calls from the NS world
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@ -64,6 +79,10 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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@ -84,6 +103,30 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
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tegra_memctrl_videomem_setup(x1, x2);
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SMC_RET1(handle, 0);
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break;
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case TEGRA_SIP_AARCH_SWITCH:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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if (!x1 || x2 > NS_SWITCH_AARCH32) {
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ERROR("%s: invalid parameters\n", __func__);
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SMC_RET1(handle, SMC_UNK);
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}
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/* x1 = ns entry point */
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cm_set_elr_spsr_el3(NON_SECURE, x1,
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(x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
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/* switch NS world mode */
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cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
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INFO("CPU switched to AARCH%s mode\n",
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(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
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SMC_RET1(handle, 0);
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break;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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83
plat/nvidia/tegra/include/t132/tegra_def.h
Normal file
83
plat/nvidia/tegra/include/t132/tegra_def.h
Normal file
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TEGRA_DEF_H__
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#define __TEGRA_DEF_H__
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#include <platform_def.h>
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/*******************************************************************************
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* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call as the `state-id` field in the 'power state' parameter.
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******************************************************************************/
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#define PLAT_SYS_SUSPEND_STATE_ID 0xD
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/*******************************************************************************
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* GIC memory map
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******************************************************************************/
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#define TEGRA_GICD_BASE 0x50041000
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#define TEGRA_GICC_BASE 0x50042000
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x60005010
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE 0x60006000
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/*******************************************************************************
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* Tegra Flow Controller constants
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******************************************************************************/
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#define TEGRA_FLOWCTRL_BASE 0x60007000
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/*******************************************************************************
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* Tegra Secure Boot Controller constants
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******************************************************************************/
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#define TEGRA_SB_BASE 0x6000C200
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/*******************************************************************************
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* Tegra Exception Vectors constants
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******************************************************************************/
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#define TEGRA_EVP_BASE 0x6000F000
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE 0x7000E400
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_BASE 0x70019000
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#endif /* __TEGRA_DEF_H__ */
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123
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
Normal file
123
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
Normal file
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@ -0,0 +1,123 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <denver.h>
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#include <debug.h>
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#include <flowctrl.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <pmc.h>
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#include <psci.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16)
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*/
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#define CPU_CMPLX_RESET_CLR 0x344
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#define CPU_CORE_RESET_MASK 0x10001
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int32_t tegra_soc_validate_power_state(unsigned int power_state)
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{
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/* Sanity check the requested afflvl */
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if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on affinity level 0 i.e.
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* a cpu on Tegra. Ignore any other affinity level.
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*/
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if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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}
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/* Sanity check the requested state id */
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if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) {
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ERROR("unsupported state id\n");
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return PSCI_E_NOT_SUPPORTED;
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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if (cpu_powergate_mask[cpu] == 0) {
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Power on CPU using PMC */
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tegra_pmc_cpu_on(cpu);
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/* Fill in the CPU powergate mask */
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cpu_powergate_mask[cpu] = 1;
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} else {
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/* Power on CPU using Flow Controller */
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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/* Nothing to be done for lower affinity levels */
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if (afflvl < MPIDR_AFFLVL2)
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return PSCI_E_SUCCESS;
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/* Enter system suspend state */
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tegra_pm_system_suspend_entry();
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/* Allow restarting CPU #1 using PMC on suspend exit */
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cpu_powergate_mask[1] = 0;
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/* Program FC to enter suspend state */
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tegra_fc_cpu_idle(read_mpidr());
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/* Suspend DCO operations */
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write_actlr_el1(id);
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return PSCI_E_SUCCESS;
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}
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97
plat/nvidia/tegra/soc/t132/plat_secondary.c
Normal file
97
plat/nvidia/tegra/soc/t132/plat_secondary.c
Normal file
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@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
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*
|
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* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
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*
|
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* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <denver.h>
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#include <mmio.h>
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#include <platform.h>
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#include <psci.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
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/* AARCH64 CPU reset vector */
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#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
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#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
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/* AARCH32 CPU reset vector */
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#define EVP_CPU_RESET_VECTOR 0x100
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extern void tegra_secure_entrypoint(void);
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/*
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* For T132, CPUs reset to AARCH32, so the reset vector is first
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* armv8_trampoline which does a warm reset to AARCH64 and starts
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* execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI.
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*/
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__aligned(8) const uint32_t armv8_trampoline[] = {
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0xE3A00003, /* mov r0, #3 */
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0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */
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0xEAFFFFFE, /* b . */
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};
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t val;
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uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
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/*
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* For T132, CPUs reset to AARCH32, so the reset vector is first
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* armv8_trampoline, which does a warm reset to AARCH64 and starts
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* execution at the address in SCRATCH34/SCRATCH35.
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*/
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INFO("Setting up T132 CPU boot\n");
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/* initial AARCH32 reset address */
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tegra_pmc_write_32(PMC_SECURE_SCRATCH22,
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(unsigned long)&armv8_trampoline);
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/* set AARCH32 exception vector (read to flush) */
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mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR,
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(unsigned long)&armv8_trampoline);
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val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR);
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/* setup secondary CPU vector */
|
||||
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
|
||||
(reset_addr & 0xFFFFFFFF) | 1);
|
||||
val = reset_addr >> 32;
|
||||
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
|
||||
|
||||
/* configure PMC */
|
||||
tegra_pmc_cpu_setup(reset_addr);
|
||||
tegra_pmc_lock_cpu_vectors();
|
||||
}
|
||||
65
plat/nvidia/tegra/soc/t132/plat_setup.c
Normal file
65
plat/nvidia/tegra/soc/t132/plat_setup.c
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <xlat_tables.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
/* sets of MMIO ranges setup */
|
||||
#define MMIO_RANGE_0_ADDR 0x50000000
|
||||
#define MMIO_RANGE_1_ADDR 0x60000000
|
||||
#define MMIO_RANGE_2_ADDR 0x70000000
|
||||
#define MMIO_RANGE_SIZE 0x200000
|
||||
|
||||
/*
|
||||
* Table of regions to map using the MMU.
|
||||
*/
|
||||
static const mmap_region_t tegra_mmap[] = {
|
||||
MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
{0}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Set up the pagetables as per the platform memory map & initialize the MMU
|
||||
******************************************************************************/
|
||||
const mmap_region_t *plat_get_mmio_map(void)
|
||||
{
|
||||
/* MMIO space */
|
||||
return tegra_mmap;
|
||||
}
|
||||
|
||||
uint64_t plat_get_syscnt_freq(void)
|
||||
{
|
||||
return 12000000;
|
||||
}
|
||||
46
plat/nvidia/tegra/soc/t132/platform_t132.mk
Normal file
46
plat/nvidia/tegra/soc/t132/platform_t132.mk
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# Redistributions of source code must retain the above copyright notice, this
|
||||
# list of conditions and the following disclaimer.
|
||||
#
|
||||
# Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# Neither the name of ARM nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific
|
||||
# prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
TEGRA_BOOT_UART_BASE := 0x70006300
|
||||
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
|
||||
|
||||
TZDRAM_BASE := 0xF1C00000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
||||
PLATFORM_CLUSTER_COUNT := 1
|
||||
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
||||
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/denver.S \
|
||||
${SOC_DIR}/plat_psci_handlers.c \
|
||||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c
|
||||
Loading…
Add table
Reference in a new issue