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feat(hikey960): define a datastore for SPMC_AT_EL3
Kinibi now has 60MB (instead of 64MB). Increase XLAT tables for BL31 Change-Id: I6843d26198a7d8bdb812e394e4482b1c35afa4c0 Signed-off-by: vallau01 <valentin.laurent@trustonic.com> Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
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5 changed files with 70 additions and 4 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -20,6 +20,7 @@
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <hi3660.h>
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@ -119,6 +120,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void bl31_plat_arch_setup(void)
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{
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#if SPMC_AT_EL3
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mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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#endif
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hikey960_init_mmu_el3(BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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BL_CODE_BASE,
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@ -156,6 +162,28 @@ static void hikey960_iomcu_dma_init(void)
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}
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}
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#if SPMC_AT_EL3
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/*
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* On the hikey960 platform when using the EL3 SPMC implementation allocate the
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* datastore for tracking shared memory descriptors in the RAM2 DRAM section
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* to ensure sufficient storage can be allocated.
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* Provide an implementation of the accessor method to allow the datastore
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* details to be retrieved by the SPMC.
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* The SPMC will take care of initializing the memory region.
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*/
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#define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024)
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__section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE];
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int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
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{
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*datastore = plat_spmc_shmem_datastore;
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*size = SPMC_SHARED_MEMORY_OBJ_SIZE;
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return 0;
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}
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#endif
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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@ -24,13 +24,16 @@
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* DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several
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* regions:
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* - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE
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* - Secure DDR (default is the top 64MB) used by OP-TEE
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* - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31
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* - Secure DDR (default is the top 60MB) used by OP-TEE
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR (8MB) reserved for OP-TEE's future use
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*/
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#define DDR_SEC_SIZE 0x04000000 /* reserve 64MB secure memory */
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#define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */
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#define DDR_SEC_BASE 0x3F000000
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#define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */
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#define DDR2_SEC_BASE 0x42C00000
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#define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */
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#define DDR_SEC_CONFIG_BASE 0x43000000
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22
plat/hisilicon/hikey960/include/plat.ld.S
Normal file
22
plat/hisilicon/hikey960/include/plat.ld.S
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/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_LD_S
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#define PLAT_LD_S
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#include <lib/xlat_tables/xlat_tables_defs.h>
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MEMORY {
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RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE
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}
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SECTIONS
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{
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ram2_region (NOLOAD) : {
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*(ram2_region)
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}>RAM2
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}
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#endif /* PLAT_LD_S */
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@ -121,10 +121,18 @@
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#define MAX_XLAT_TABLES 3
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#endif
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#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
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#if defined(IMAGE_BL2)
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#define MAX_XLAT_TABLES 5
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#endif
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#if defined(IMAGE_BL31)
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#if defined(SPMC_AT_EL3)
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#define MAX_XLAT_TABLES 17
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#else
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#define MAX_XLAT_TABLES 5
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#endif
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#endif
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#define MAX_MMAP_REGIONS 16
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/*
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@ -164,6 +164,11 @@ FIP_ALIGN := 512
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# SPM dispatcher
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ifeq (${SPD},spmd)
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ifeq (${SPMC_AT_EL3},1)
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# Add support for platform supplied linker script for BL31 build
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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endif
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ifeq ($(PLAT_SP_MANIFEST_DTS),)
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$(error "Error: A SP manifest is required for the SPMC.")
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endif
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