diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c new file mode 100644 index 000000000..862894857 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static void dcm_infra(bool on) +{ + dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(on); +} + +static void dcm_mcusys(bool on) +{ + dcm_mcusys_par_wrap_mcu_misc_dcm(on); +} + +static void dcm_mcusys_acp(bool on) +{ + dcm_mcusys_par_wrap_mcu_acp_dcm(on); +} + +static void dcm_mcusys_adb(bool on) +{ + dcm_mcusys_par_wrap_mcu_adb_dcm(on); +} + +static void dcm_mcusys_apb(bool on) +{ + dcm_mcusys_par_wrap_mcu_apb_dcm(on); +} + +static void dcm_mcusys_bus(bool on) +{ + dcm_mcusys_par_wrap_mcu_bus_qdcm(on); +} + +static void dcm_mcusys_cbip(bool on) +{ + dcm_mcusys_par_wrap_mcu_cbip_dcm(on); +} + +static void dcm_mcusys_chi_mon(bool on) +{ + dcm_mcusys_par_wrap_mcu_chi_mon_dcm(on); +} + +static void dcm_mcusys_core(bool on) +{ + dcm_mcusys_par_wrap_mcu_core_qdcm(on); +} + +static void dcm_mcusys_dsu_acp(bool on) +{ + dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(on); +} + +static void dcm_mcusys_ebg(bool on) +{ + dcm_mcusys_par_wrap_mcu_ebg_dcm(on); +} + +static void dcm_mcusys_gic_spi(bool on) +{ + dcm_mcusys_par_wrap_mcu_gic_spi_dcm(on); +} + +static void dcm_mcusys_io(bool on) +{ + dcm_mcusys_par_wrap_mcu_io_dcm(on); +} + +static void dcm_mcusys_l3c(bool on) +{ + dcm_mcusys_par_wrap_mcu_l3c_dcm(on); +} + +static void dcm_mcusys_stall(bool on) +{ + dcm_mcusys_par_wrap_mcu_stalldcm(on); +} + +static void dcm_vlp(bool on) +{ + dcm_vlp_ao_bcrm_vlp_bus_dcm(on); +} + +int mtk_dcm_init(void) +{ + dcm_infra(true); + dcm_mcusys(true); + dcm_mcusys_acp(true); + dcm_mcusys_adb(true); + dcm_mcusys_apb(true); + dcm_mcusys_bus(true); + dcm_mcusys_cbip(true); + dcm_mcusys_chi_mon(true); + dcm_mcusys_core(true); + dcm_mcusys_dsu_acp(true); + dcm_mcusys_ebg(true); + dcm_mcusys_gic_spi(true); + dcm_mcusys_io(true); + dcm_mcusys_l3c(true); + dcm_mcusys_stall(true); + dcm_vlp(true); + + return 0; +} + +MTK_PLAT_SETUP_0_INIT(mtk_dcm_init); diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c new file mode 100644 index 000000000..d63755384 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static const mmap_region_t dcm_mmap[] = { + MAP_REGION_FLAT(MCUSYS_PAR_WRAP_BASE, MCUSYS_PAR_WRAP_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_IO_CTRL_AO, APINFRA_IO_CTRL_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_IO_NOC_AO, APINFRA_IO_NOC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_MEM_INTF_NOC_AO, APINFRA_MEM_INTF_NOC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_MEM_CTRL_AO, APINFRA_MEM_CTRL_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(PERI_AO_BCRM_BASE, PERI_AO_BCRM_BASE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(VLP_AO_BCRM_BASE, VLP_AO_BCRM_BASE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; +DECLARE_MTK_MMAP_REGIONS(dcm_mmap); + +static bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int state) +{ + return ((mmio_read_32(addr) & mask) == state); +} + +bool dcm_mcusys_par_wrap_mcu_l3c_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_l3c_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_acp_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_acp_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_adb_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_adb_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_stalldcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_stalldcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_apb_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_apb_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_io_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_io_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_bus_qdcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_bus_qdcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_core_qdcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_core_qdcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm1_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_bkr_ldcm1(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm2_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_bkr_ldcm2(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_cbip_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_cbip_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_misc_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_misc_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_dsu_acp_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_chi_mon_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_chi_mon_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_gic_spi_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_gic_spi_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_ebg_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_ebg_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON); + + return ret; +} + +void dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON); + } else { + mmio_clrsetbits_32(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_OFF); + } +} + +bool dcm_peri_ao_bcrm_peri_bus1_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + + return ret; +} + +void dcm_peri_ao_bcrm_peri_bus1_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + } else { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF); + } +} + +bool dcm_peri_ao_bcrm_peri_bus2_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + + return ret; +} + +void dcm_peri_ao_bcrm_peri_bus2_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + } else { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF); + } +} + +bool dcm_vlp_ao_bcrm_vlp_bus_dcm_is_on(void) +{ + return dcm_check_state(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON); +} + +void dcm_vlp_ao_bcrm_vlp_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_OFF); +} diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h new file mode 100644 index 000000000..3d7a60c28 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DCM_MTK_DCM_UTILS_H_ +#define DCM_MTK_DCM_UTILS_H_ + +#include + +#include + +#define MCUSYS_PAR_WRAP_BASE (MCUCFG_BASE + 0x001B0000) +#define MCUSYS_PAR_WRAP_SIZE (0x10000) +#define APINFRA_IO_CTRL_AO (IO_PHYS + 0x00156000) +#define APINFRA_IO_CTRL_AO_SIZE (0x1000) +#define APINFRA_IO_NOC_AO (IO_PHYS + 0x04012000) +#define APINFRA_IO_NOC_AO_SIZE (0x1000) +#define APINFRA_MEM_INTF_NOC_AO (IO_PHYS + 0x04032000) +#define APINFRA_MEM_INTF_NOC_AO_SIZE (0x1000) +#define APINFRA_MEM_CTRL_AO (IO_PHYS + 0x04124000) +#define APINFRA_MEM_CTRL_AO_SIZE (0x1000) +#define PERI_AO_BCRM_BASE (IO_PHYS + 0x06610000) +#define PERI_AO_BCRM_BASE_SIZE (0x1000) +#define VLP_AO_BCRM_BASE (IO_PHYS + 0x0c030000) +#define VLP_AO_BCRM_BASE_SIZE (0x1000) + +#define MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x78) +#define MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x270) +#define MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x278) +#define MCUSYS_PAR_WRAP_MP0_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x27c) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x280) +#define MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x294) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG1 (MCUSYS_PAR_WRAP_BASE + 0x284) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG2 (MCUSYS_PAR_WRAP_BASE + 0x288) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG3 (MCUSYS_PAR_WRAP_BASE + 0x28c) +#define MCUSYS_PAR_WRAP_CI700_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x298) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a0) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a4) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a8) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2ac) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2b0) +#define MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x2b4) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG \ + (MCUSYS_PAR_WRAP_BASE + 0x2bc) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG \ + (MCUSYS_PAR_WRAP_BASE + 0x2c4) +#define MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG \ + (MCUSYS_PAR_WRAP_BASE + 0x2b8) +#define MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x2dc) +#define MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG (MCUSYS_PAR_WRAP_BASE + 0x2e0) +#define MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG (MCUSYS_PAR_WRAP_BASE + 0x404) +#define CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0 \ + (APINFRA_IO_CTRL_AO + 0x8) +#define CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0 \ + (APINFRA_IO_NOC_AO + 0x4) +#define VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0 \ + (APINFRA_MEM_INTF_NOC_AO + 0x0) +#define CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ + (APINFRA_MEM_CTRL_AO + 0xc) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ + (APINFRA_MEM_CTRL_AO + 0x14) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1 \ + (APINFRA_MEM_CTRL_AO + 0x18) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2 \ + (APINFRA_MEM_CTRL_AO + 0x1c) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3 \ + (APINFRA_MEM_CTRL_AO + 0x20) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4 \ + (APINFRA_MEM_CTRL_AO + 0x24) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5 \ + (APINFRA_MEM_CTRL_AO + 0x28) + +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0 (PERI_AO_BCRM_BASE + 0x2c) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1 (PERI_AO_BCRM_BASE + 0x30) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2 (PERI_AO_BCRM_BASE + 0x34) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3 (PERI_AO_BCRM_BASE + 0x38) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0 (PERI_AO_BCRM_BASE + 0x20) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1 (PERI_AO_BCRM_BASE + 0x24) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2 (PERI_AO_BCRM_BASE + 0x28) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3 (PERI_AO_BCRM_BASE + 0x2c) +#define VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0 (VLP_AO_BCRM_BASE + 0x5c) + +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK 0x10001 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON 0x10001 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK 0x1FFF07FF +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON 0x1FFF07FF +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK 0xFF +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON 0xFF +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK 0x1FFFF00 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON 0x1FFFF00 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK 0x1001 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON 0x1001 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK 0x1110000 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK 0x1111 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON 0x1110000 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON 0x1111 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK 0x11111111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK 0x1111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON 0x11111111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON 0x1111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK 0XFFFF0003 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON 0x8A080002 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_OFF 0x8A080000 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK 0x3 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK 0x7 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON 0x7 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_OFF 0x3 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK 0x1E +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_OFF 0x1E +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK BIT(2) +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_OFF BIT(2) +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x14 +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x14 +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x1C +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK 0x90 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK BIT(21) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK BIT(22) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK BIT(20) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK BIT(24) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK BIT(23) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x1C +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON 0x90 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON BIT(21) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON BIT(22) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON BIT(20) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON BIT(24) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON BIT(23) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK 0x14920 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON 0x14920 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF 0 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK 0x7C026 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON 0x26 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_OFF 0x6 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK (0xFFFF0003) +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON (0x8A080003) +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_OFF (0xA0880000) + +void dcm_mcusys_par_wrap_mcu_l3c_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_l3c_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_acp_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_acp_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_adb_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_adb_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_stalldcm(bool on); +bool dcm_mcusys_par_wrap_mcu_stalldcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_apb_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_apb_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_io_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_io_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_bus_qdcm(bool on); +bool dcm_mcusys_par_wrap_mcu_bus_qdcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_core_qdcm(bool on); +bool dcm_mcusys_par_wrap_mcu_core_qdcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_bkr_ldcm1(bool on); +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm1_is_on(void); +void dcm_mcusys_par_wrap_mcu_bkr_ldcm2(bool on); +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm2_is_on(void); +void dcm_mcusys_par_wrap_mcu_cbip_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_cbip_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_misc_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_misc_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_dsu_acp_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_chi_mon_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_chi_mon_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_gic_spi_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_gic_spi_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_ebg_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_ebg_dcm_is_on(void); +void dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm_is_on(void); +void dcm_peri_ao_bcrm_peri_bus1_dcm(bool on); +bool dcm_peri_ao_bcrm_peri_bus1_dcm_is_on(void); +void dcm_peri_ao_bcrm_peri_bus2_dcm(bool on); +bool dcm_peri_ao_bcrm_peri_bus2_dcm_is_on(void); +void dcm_vlp_ao_bcrm_vlp_bus_dcm(bool on); +bool dcm_vlp_ao_bcrm_vlp_bus_dcm_is_on(void); + +#endif /* DCM_MTK_DCM_UTILS_H_ */ diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk index 8ae8e285d..a43050b08 100644 --- a/plat/mediatek/mt8196/platform.mk +++ b/plat/mediatek/mt8196/platform.mk @@ -18,6 +18,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common \ -I${MTK_PLAT}/include \ -I${MTK_PLAT}/include/${ARCH_VERSION} \ -I${MTK_PLAT} \ + -I${MTK_PLAT_SOC}/drivers/dcm/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/include \ -Idrivers/arm/gic \ @@ -57,6 +58,8 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/params_setup.c \ ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + $(MTK_PLAT)/$(MTK_SOC)/drivers/dcm/mtk_dcm.c \ + $(MTK_PLAT)/$(MTK_SOC)/drivers/dcm/mtk_dcm_utils.c \ $(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \ $(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c