From a12cb77c820dfed9b05aff6245acb4295cb02b87 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Mon, 20 Feb 2023 10:50:15 +0000 Subject: [PATCH 1/4] refactor(qemu): make use of setup_page_tables() Use the setup_page_tables() helper function to setup page tables. Signed-off-by: Chen Baozi Change-Id: I0bca4e463ed68abf2ef1c79fc8e5cb2b635fcd1c --- plat/qemu/common/qemu_bl1_setup.c | 39 ++++++++++++++++++++++---- plat/qemu/common/qemu_bl2_setup.c | 45 ++++++++++++++++++++++-------- plat/qemu/common/qemu_bl31_setup.c | 34 +++++++++++++++++++--- plat/qemu/common/qemu_common.c | 43 ++++------------------------ plat/qemu/common/qemu_private.h | 17 ++--------- 5 files changed, 105 insertions(+), 73 deletions(-) diff --git a/plat/qemu/common/qemu_bl1_setup.c b/plat/qemu/common/qemu_bl1_setup.c index 67f33273f..a3f61732d 100644 --- a/plat/qemu/common/qemu_bl1_setup.c +++ b/plat/qemu/common/qemu_bl1_setup.c @@ -14,6 +14,27 @@ #include "qemu_private.h" +#define MAP_BL1_TOTAL MAP_REGION_FLAT( \ + bl1_tzram_layout.total_base, \ + bl1_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#define MAP_BL1_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL1_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT( \ + BL1_RO_DATA_BASE, \ + BL1_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) + +#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) + /* Data structure which holds the extents of the trusted SRAM for BL1*/ static meminfo_t bl1_tzram_layout; @@ -49,11 +70,19 @@ void bl1_early_platform_setup(void) void bl1_plat_arch_setup(void) { - QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - BL_CODE_BASE, BL1_CODE_END, - BL1_RO_DATA_BASE, BL1_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); + const mmap_region_t bl_regions[] = { + MAP_BL1_TOTAL, + MAP_BL1_RO, + MAP_BL_COHERENT_RAM, + {0} + }; + + setup_page_tables(bl_regions, plat_qemu_get_mmap()); +#ifdef __aarch64__ + enable_mmu_el3(0); +#else + enable_mmu_svc_mon(0); +#endif } void bl1_platform_setup(void) diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c index be5587714..8f6066bb5 100644 --- a/plat/qemu/common/qemu_bl2_setup.c +++ b/plat/qemu/common/qemu_bl2_setup.c @@ -23,6 +23,26 @@ #include "qemu_private.h" +#define MAP_BL2_TOTAL MAP_REGION_FLAT( \ + bl2_tzram_layout.total_base, \ + bl2_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_BL2_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); @@ -83,19 +103,22 @@ void bl2_platform_setup(void) /* TODO Initialize timer */ } -#ifdef __aarch64__ -#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__) -#else -#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) -#endif - void bl2_plat_arch_setup(void) { - QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); + const mmap_region_t bl_regions[] = { + MAP_BL2_TOTAL, + MAP_BL2_RO, + MAP_BL_COHERENT_RAM, + {0} + }; + + setup_page_tables(bl_regions, plat_qemu_get_mmap()); + +#ifdef __aarch64__ + enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); +#endif } /******************************************************************************* diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c index 4f60eb163..3195d9158 100644 --- a/plat/qemu/common/qemu_bl31_setup.c +++ b/plat/qemu/common/qemu_bl31_setup.c @@ -12,6 +12,26 @@ #include "qemu_private.h" +#define MAP_BL31_TOTAL MAP_REGION_FLAT( \ + BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | EL3_PAS) +#define MAP_BL31_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) + +#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) + /* * Placeholder variables for copying the arguments that have been passed to * BL3-1 from BL2. @@ -64,10 +84,16 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE), - BL_CODE_BASE, BL_CODE_END, - BL_RO_DATA_BASE, BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, + MAP_BL_COHERENT_RAM, + {0} + }; + + setup_page_tables(bl_regions, plat_qemu_get_mmap()); + + enable_mmu_el3(0); } static void qemu_gpio_init(void) diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c index 23ac5813e..935ba7a77 100644 --- a/plat/qemu/common/qemu_common.c +++ b/plat/qemu/common/qemu_common.c @@ -122,45 +122,12 @@ static const mmap_region_t plat_qemu_mmap[] = { #endif /******************************************************************************* - * Macro generating the code for the function setting up the pagetables as per - * the platform memory map & initialize the mmu, for the given exception level + * Returns QEMU platform specific memory map regions. ******************************************************************************/ - -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void qemu_configure_mmu_##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long code_start, \ - unsigned long code_limit, \ - unsigned long ro_start, \ - unsigned long ro_limit, \ - unsigned long coh_start, \ - unsigned long coh_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(code_start, code_start, \ - code_limit - code_start, \ - MT_CODE | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_RO_DATA | MT_SECURE); \ - mmap_add_region(coh_start, coh_start, \ - coh_limit - coh_start, \ - MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(plat_qemu_mmap); \ - init_xlat_tables(); \ - \ - enable_mmu_##_el(0); \ - } - -/* Define EL1 and EL3 variants of the function initialising the MMU */ -#ifdef __aarch64__ -DEFINE_CONFIGURE_MMU_EL(el1) -DEFINE_CONFIGURE_MMU_EL(el3) -#else -DEFINE_CONFIGURE_MMU_EL(svc_mon) -#endif +const mmap_region_t *plat_qemu_get_mmap(void) +{ + return plat_qemu_mmap; +} #if MEASURED_BOOT || TRUSTED_BOARD_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h index 159c44f7a..199ca018e 100644 --- a/plat/qemu/common/qemu_private.h +++ b/plat/qemu/common/qemu_private.h @@ -9,26 +9,13 @@ #include -void qemu_configure_mmu_svc_mon(unsigned long total_base, - unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); - -void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); - -void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, - unsigned long code_start, unsigned long code_limit, - unsigned long ro_start, unsigned long ro_limit, - unsigned long coh_start, unsigned long coh_limit); +#include void plat_qemu_io_setup(void); int qemu_io_register_sp_pkg(const char *name, const char *uuid, uintptr_t load_addr); unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); +const mmap_region_t *plat_qemu_get_mmap(void); void qemu_console_init(void); From af994ae8a089ead6082ca82036d30074f554ed52 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Sun, 12 Mar 2023 20:58:04 +0800 Subject: [PATCH 2/4] feat(qemu): make coherent memory section optional Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent memory section is not required for them and should be an optional section. Signed-off-by: Chen Baozi Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129 --- plat/qemu/common/qemu_bl1_setup.c | 4 ++++ plat/qemu/common/qemu_bl2_setup.c | 4 ++++ plat/qemu/common/qemu_bl31_setup.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/plat/qemu/common/qemu_bl1_setup.c b/plat/qemu/common/qemu_bl1_setup.c index a3f61732d..529510ce4 100644 --- a/plat/qemu/common/qemu_bl1_setup.c +++ b/plat/qemu/common/qemu_bl1_setup.c @@ -29,11 +29,13 @@ - BL_RO_DATA_BASE, \ MT_RO_DATA | EL3_PAS) +#if USE_COHERENT_MEM #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ BL_COHERENT_RAM_BASE, \ BL_COHERENT_RAM_END \ - BL_COHERENT_RAM_BASE, \ MT_DEVICE | MT_RW | EL3_PAS) +#endif /* Data structure which holds the extents of the trusted SRAM for BL1*/ static meminfo_t bl1_tzram_layout; @@ -73,7 +75,9 @@ void bl1_plat_arch_setup(void) const mmap_region_t bl_regions[] = { MAP_BL1_TOTAL, MAP_BL1_RO, +#if USE_COHERENT_MEM MAP_BL_COHERENT_RAM, +#endif {0} }; diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c index 8f6066bb5..c4d235e0a 100644 --- a/plat/qemu/common/qemu_bl2_setup.c +++ b/plat/qemu/common/qemu_bl2_setup.c @@ -38,11 +38,13 @@ - BL_RO_DATA_BASE, \ MT_RO_DATA | MT_SECURE) +#if USE_COHERENT_MEM #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ BL_COHERENT_RAM_BASE, \ BL_COHERENT_RAM_END \ - BL_COHERENT_RAM_BASE, \ MT_DEVICE | MT_RW | MT_SECURE) +#endif /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); @@ -108,7 +110,9 @@ void bl2_plat_arch_setup(void) const mmap_region_t bl_regions[] = { MAP_BL2_TOTAL, MAP_BL2_RO, +#if USE_COHERENT_MEM MAP_BL_COHERENT_RAM, +#endif {0} }; diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c index 3195d9158..0b84e9620 100644 --- a/plat/qemu/common/qemu_bl31_setup.c +++ b/plat/qemu/common/qemu_bl31_setup.c @@ -26,11 +26,13 @@ - BL_RO_DATA_BASE, \ MT_RO_DATA | EL3_PAS) +#if USE_COHERENT_MEM #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ BL_COHERENT_RAM_BASE, \ BL_COHERENT_RAM_END \ - BL_COHERENT_RAM_BASE, \ MT_DEVICE | MT_RW | EL3_PAS) +#endif /* * Placeholder variables for copying the arguments that have been passed to @@ -87,7 +89,9 @@ void bl31_plat_arch_setup(void) const mmap_region_t bl_regions[] = { MAP_BL31_TOTAL, MAP_BL31_RO, +#if USE_COHERENT_MEM MAP_BL_COHERENT_RAM, +#endif {0} }; From 226f4c8e35c4441e80ad523b9105eab4ca630396 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Wed, 22 Feb 2023 06:58:39 +0000 Subject: [PATCH 3/4] feat(qemu): add "neoverse-n1" cpu support Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref') platform. Signed-off-by: Chen Baozi Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f --- plat/qemu/qemu_sbsa/platform.mk | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index 2393b397d..fec83db56 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -19,6 +19,11 @@ endif # Enable new version of image loading on QEMU platforms LOAD_IMAGE_V2 := 1 +CTX_INCLUDE_AARCH32_REGS := 0 +ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) +$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") +endif + ifeq ($(NEED_BL32),yes) $(eval $(call add_define,QEMU_LOAD_BL32)) endif @@ -36,6 +41,18 @@ PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ drivers/arm/pl011/${ARCH}/pl011_console.S +# Treating this as a memory-constrained port for now +USE_COHERENT_MEM := 0 + +# This can be overridden depending on CPU(s) used in the QEMU image +HW_ASSISTED_COHERENCY := 1 + +QEMU_CPU_LIBS := lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + lib/cpus/aarch64/neoverse_n_common.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/qemu_max.S + include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} @@ -49,9 +66,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c -BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \ - lib/cpus/aarch64/cortex_a72.S \ - lib/cpus/aarch64/qemu_max.S \ +BL1_SOURCES += ${QEMU_CPU_LIBS} BL2_SOURCES += drivers/io/io_semihosting.c \ drivers/io/io_storage.c \ @@ -77,9 +92,7 @@ QEMU_GIC_SOURCES := ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c -BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \ - lib/cpus/aarch64/cortex_a72.S \ - lib/cpus/aarch64/qemu_max.S \ +BL31_SOURCES += ${QEMU_CPU_LIBS} \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ plat/common/plat_psci_common.c \ From 6b66693685f828a51c7f78bfa402d6b192169a6d Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Sun, 12 Mar 2023 23:19:28 +0800 Subject: [PATCH 4/4] feat(qemu): add A76/N1 cpu support for virt Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt') platform. Signed-off-by: Chen Baozi Change-Id: I77a3e0bb8397a2fb45a2caa7d93ba38e39297f93 --- plat/qemu/qemu/platform.mk | 42 +++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk index 4cbce9d04..92b41ef77 100644 --- a/plat/qemu/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -18,6 +18,17 @@ $(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER)) $(eval $(call add_define,ARMV7_SUPPORTS_VFP)) # Qemu expects a BL32 boot stage. NEED_BL32 := yes +else +CTX_INCLUDE_AARCH32_REGS := 0 +ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) +$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") +endif + +# Treating this as a memory-constrained port for now +USE_COHERENT_MEM := 0 + +# This can be overridden depending on CPU(s) used in the QEMU image +HW_ASSISTED_COHERENCY := 1 endif # ARMv7 ifeq (${SPD},opteed) @@ -46,6 +57,17 @@ PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ ifeq (${ARM_ARCH_MAJOR},8) PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} + +QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/neoverse_n_common.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/qemu_max.S +else +QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S endif PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ @@ -135,18 +157,8 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ - ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c - -ifeq (${ARM_ARCH_MAJOR},8) -BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ - lib/cpus/aarch64/cortex_a72.S \ - lib/cpus/aarch64/qemu_max.S \ - -else -BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S -endif + ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \ + ${QEMU_CPU_LIBS} BL2_SOURCES += drivers/io/io_semihosting.c \ drivers/io/io_storage.c \ @@ -195,11 +207,7 @@ $(error "Incorrect GIC driver chosen for QEMU platform") endif ifeq (${ARM_ARCH_MAJOR},8) -BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ - lib/cpus/aarch64/cortex_a72.S \ - lib/cpus/aarch64/qemu_max.S \ +BL31_SOURCES += ${QEMU_CPU_LIBS} \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ plat/common/plat_psci_common.c \