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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(plat/nxp/ls1043ardb): add ls1043ardb board support
The LS1043A reference design board (RDB) is a computing, evaluation, and development platform that supports the Layerscape LS1043A architecture processor. The old implementation in tf-a (plat/layerscape/board/ls1043/) is removed, and this patch is adding it back, it is using the unified software component and architecture with all the other Layerscape platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Change-Id: I83eee2f9254267b148960b05e25b6c9ba86cf07e
This commit is contained in:
Jiafei Pan
parent
3b0de91825
commit
e4bd65fed8
6 changed files with 335 additions and 0 deletions
159
plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
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159
plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <errata.h>
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_1600 = {
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.cs[0].config = U(0x80040322),
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.cs[0].bnds = U(0x7F),
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.sdram_cfg[0] = U(0xC50C0000),
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.sdram_cfg[1] = U(0x401100),
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.timing_cfg[0] = U(0x91550018),
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.timing_cfg[1] = U(0xBBB48C42),
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.timing_cfg[2] = U(0x48C111),
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.timing_cfg[3] = U(0x10C1000),
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.timing_cfg[4] = U(0x2),
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.timing_cfg[5] = U(0x3401400),
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.timing_cfg[7] = U(0x13300000),
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.timing_cfg[8] = U(0x2115600),
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.sdram_mode[0] = U(0x3010210),
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.sdram_mode[9] = U(0x4000000),
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.sdram_mode[8] = U(0x500),
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.sdram_mode[2] = U(0x10210),
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.sdram_mode[10] = U(0x400),
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.sdram_mode[11] = U(0x4000000),
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.sdram_mode[4] = U(0x10210),
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.sdram_mode[12] = U(0x400),
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.sdram_mode[13] = U(0x4000000),
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.sdram_mode[6] = U(0x10210),
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.sdram_mode[14] = U(0x400),
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.sdram_mode[15] = U(0x4000000),
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.interval = U(0x18600618),
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.zq_cntl = U(0x8A090705),
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.clk_cntl = U(0x3000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xA181),
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.wrlvl_cntl[0] = U(0x8675F607),
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.wrlvl_cntl[1] = U(0x7090807,
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.wrlvl_cntl[2] = U(0x7070707),
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.debug[28] = U(0x00700046),
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};
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uint64_t board_static_ddr(struct ddr_info *priv)
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{
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memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
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return ULL(0x80000000);
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}
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#else
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static const struct rc_timing rcz[] = {
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{1600, 12, 7},
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{}
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};
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static const struct board_timing ram[] = {
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{0x1f, rcz, 0x00020100, 0},
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};
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int ddr_board_options(struct ddr_info *priv)
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{
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int ret;
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struct memctl_opt *popts = &priv->opt;
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ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
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if (ret)
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return ret;
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popts->cpo_sample = U(0x46);
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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return 0;
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}
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/* DDR model number: MT40A512M8HX-093E */
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struct dimm_params ddr_raw_timing = {
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.n_ranks = U(1),
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.rank_density = ULL(2147483648),
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.capacity = ULL(2147483648),
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.primary_sdram_width = U(32),
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.n_row_addr = U(15),
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.n_col_addr = U(10),
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.bank_group_bits = U(2),
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.burst_lengths_bitmask = U(0x0c),
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.tckmin_x_ps = 938,
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.tckmax_ps = 1500,
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.caslat_x = U(0x000DFA00),
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.taa_ps = 13500,
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.trcd_ps = 13500,
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.trp_ps = 13500,
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.tras_ps = 33000,
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.trc_ps = 46500,
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.twr_ps = 15000,
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.trfc1_ps = 260000,
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.trfc2_ps = 160000,
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.trfc4_ps = 110000,
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.tfaw_ps = 21000,
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.trrds_ps = 3700,
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.trrdl_ps = 5300,
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.tccdl_ps = 5355,
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.refresh_rate_ps = U(7800000),
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.rc = U(0x1f),
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};
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int ddr_get_ddr_params(struct dimm_params *pdimm,
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struct ddr_conf *conf)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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conf->dimm_in_use[0] = 1;
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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return 1;
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}
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#endif
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int64_t init_ddr(void)
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{
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struct ddr_info info;
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struct sysinfo sys;
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int64_t dram_size;
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zeromem(&sys, sizeof(sys));
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get_clocks(&sys);
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(struct ddr_info));
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info.num_ctlrs = 1;
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info.dimm_on_ctlr = 1;
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info.clk = get_ddr_freq(&sys, 0);
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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dram_size = dram_init(&info);
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if (dram_size < 0) {
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ERROR("DDR init failed\n");
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}
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#ifdef ERRATA_SOC_A008850
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erratum_a008850_post();
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#endif
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return dram_size;
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}
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79
plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
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79
plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DEF_H
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#define PLAT_DEF_H
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#include <arch.h>
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/*
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* Required without TBBR.
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* To include the defines for DDR PHY Images.
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*/
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#include <tbbr_img_def.h>
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#include "policy.h"
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#include <soc.h>
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#define NXP_SPD_EEPROM0 0x51
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#define NXP_SYSCLK_FREQ 100000000
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#define NXP_DDRCLK_FREQ 100000000
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/* UART related definition */
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#define NXP_CONSOLE_ADDR NXP_UART_ADDR
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#define NXP_CONSOLE_BAUDRATE 115200
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL2)
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#if defined(TRUSTED_BOARD_BOOT)
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#define PLATFORM_STACK_SIZE 0x2000
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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/* SD block buffer */
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#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
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#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
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/* IO defines as needed by IO driver framework */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_BLOCK_DEVICES 1
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#define MAX_IO_HANDLES 4
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/*
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* FIP image defines - Offset at which FIP Image would be present
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* Image would include Bl31 , Bl33 and Bl32 (optional)
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*/
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#ifdef POLICY_FUSE_PROVISION
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#define MAX_FIP_DEVICES 2
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#endif
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#ifndef MAX_FIP_DEVICES
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#define MAX_FIP_DEVICES 1
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#endif
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/*
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* ID of the secure physical generic timer interrupt used by the BL32.
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*/
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#define BL32_IRQ_SEC_PHY_TIMER 29
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_LS_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_LS_G0_IRQ_PROPS(grp)
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#endif /* PLAT_DEF_H */
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28
plat/nxp/soc-ls1043a/ls1043ardb/platform.c
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plat/nxp/soc-ls1043a/ls1043ardb/platform.c
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/*
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* Copyright 2020-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat_common.h>
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#pragma weak board_enable_povdd
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#pragma weak board_disable_povdd
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bool board_enable_povdd(void)
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{
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#ifdef CONFIG_POVDD_ENABLE
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return true;
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#else
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return false;
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#endif
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}
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bool board_disable_povdd(void)
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{
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#ifdef CONFIG_POVDD_ENABLE
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return true;
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#else
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return false;
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#endif
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}
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40
plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
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40
plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
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#
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# Copyright 2018-2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# board-specific build parameters
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BOOT_MODE ?= nor
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BOARD := ls1043ardb
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POVDD_ENABLE := no
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# DDR Compilation Configs
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CONFIG_DDR_NODIMM := 1
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NUM_OF_DDRC := 1
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DDRC_NUM_DIMM := 0
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DDRC_NUM_CS := 4
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DDR_ECC_EN := no
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CONFIG_STATIC_DDR := 0
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# On-Board Flash Details
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# 128MB IFC NOR Flash
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NOR_FLASH_SZ := 0x8000000
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# Platform specific features.
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WARM_BOOT := no
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# Adding Platform files build files
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BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
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${BOARD_PATH}/platform.c
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SUPPORTED_BOOT_MODE := nor \
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sd \
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nand
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# Adding platform board build info
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include plat/nxp/common/plat_make_helper/plat_common_def.mk
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# Adding SoC build info
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include plat/nxp/soc-ls1043a/soc.mk
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13
plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
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plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat_def.h>
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#include <plat_default_def.h>
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#endif /* PLATFORM_DEF_H */
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16
plat/nxp/soc-ls1043a/ls1043ardb/policy.h
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16
plat/nxp/soc-ls1043a/ls1043ardb/policy.h
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef POLICY_H
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#define POLICY_H
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/*
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* Set this to 0x0 to leave the default SMMU page size in sACR
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* Set this to 0x1 to change the SMMU page size to 64K
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*/
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#define POLICY_SMMU_PAGESZ_64K 0x1
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#endif /* POLICY_H */
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