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refactor(cpus): use cpu errata wrappers for aarch64 hunter based cpus

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Adapt to use errata frame-work cpu macro helpers for following cpus:

- cortex-a520
- cortex-a720
- cortex-x4
- cortex-chaberton
- cortex-blackhawk

- Use sysreg_bit_set helper macro for enabling of any system register
  bit field.
- Use errata_report_shim macro for reporting errata.
- Use cpu_reset_func_start/end helpers for adding cpu reset functions.

Testing:

- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with erratas and stepping through from ArmDS and running tftf.

Change-Id: I954fb603aa3746e02f2288656b98148d9cfd7843
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2023-04-24 15:21:19 -05:00
parent af704705c1
commit e488307124
5 changed files with 39 additions and 131 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
lib/cpus/aarch64/cortex_a520.S
View file

@ -30,28 +30,17 @@ func cortex_a520_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_A520_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A520_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a520_core_pwr_dwn endfunc cortex_a520_core_pwr_dwn
/* errata_report_shim cortex_a520
* Errata printing function for Cortex A520. Must follow AAPCS.
*/
#if REPORT_ERRATA
func cortex_a520_errata_report
ret
endfunc cortex_a520_errata_report
#endif
func cortex_a520_reset_func cpu_reset_func_start cortex_a520
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
isb cpu_reset_func_end cortex_a520
ret
endfunc cortex_a520_reset_func
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex A520 specific * This function provides Cortex A520 specific

57
lib/cpus/aarch64/cortex_a720.S
View file

@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960 workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if WORKAROUND_CVE_2022_23960 #if IMAGE_BL31
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
func cortex_a720_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex A720 generic vectors are overridden to apply errata * The Cortex A720 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_a720 override_vector_table wa_cve_vbar_cortex_a720
msr vbar_el3, x0 #endif /* IMAGE_BL31 */
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ workaround_reset_end cortex_a720, CVE(2022, 23960)
isb check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
ret
endfunc cortex_a720_reset_func cpu_reset_func_start cortex_a720
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end cortex_a720
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -61,33 +52,13 @@ func cortex_a720_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_A720_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A720_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a720_core_pwr_dwn endfunc cortex_a720_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_a720
/*
* Errata printing function for Cortex A720. Must follow AAPCS.
*/
func cortex_a720_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a720_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex A720-specific * This function provides Cortex A720-specific

19
lib/cpus/aarch64/cortex_blackhawk.S
View file

@ -21,12 +21,10 @@
#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
func cortex_blackhawk_reset_func cpu_reset_func_start cortex_blackhawk
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
isb cpu_reset_func_end cortex_blackhawk
ret
endfunc cortex_blackhawk_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -37,21 +35,12 @@ func cortex_blackhawk_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_blackhawk_core_pwr_dwn endfunc cortex_blackhawk_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_blackhawk
/*
* Errata printing function for Cortex Blackhawk. Must follow AAPCS.
*/
func cortex_blackhawk_errata_report
ret
endfunc cortex_blackhawk_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Blackhawk specific * This function provides Cortex Blackhawk specific

19
lib/cpus/aarch64/cortex_chaberton.S
View file

@ -21,12 +21,10 @@
#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
func cortex_chaberton_reset_func cpu_reset_func_start cortex_chaberton
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
isb cpu_reset_func_end cortex_chaberton
ret
endfunc cortex_chaberton_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -37,21 +35,12 @@ func cortex_chaberton_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_chaberton_core_pwr_dwn endfunc cortex_chaberton_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_chaberton
/*
* Errata printing function for Cortex Chaberton. Must follow AAPCS.
*/
func cortex_chaberton_errata_report
ret
endfunc cortex_chaberton_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Chaberton specific * This function provides Cortex Chaberton specific

56
lib/cpus/aarch64/cortex_x4.S
View file

@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960 workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if WORKAROUND_CVE_2022_23960 #if IMAGE_BL31
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
func cortex_x4_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex X4 generic vectors are overridden to apply errata * The Cortex X4 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_x4 override_vector_table wa_cve_vbar_cortex_x4
msr vbar_el3, x0 #endif /* IMAGE_BL31 */
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ workaround_reset_end cortex_x4, CVE(2022, 23960)
isb check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
ret
endfunc cortex_x4_reset_func cpu_reset_func_start cortex_x4
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end cortex_x4
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
@ -61,33 +52,12 @@ func cortex_x4_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_X4_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_X4_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_x4_core_pwr_dwn endfunc cortex_x4_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_x4
/*
* Errata printing function for Cortex X4. Must follow AAPCS.
*/
func cortex_x4_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_x4, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_x4_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex X4-specific * This function provides Cortex X4-specific