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feat(mt8186): add DFD control in SiP service

Browse source 
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I659ea1e0789cf135a71a13b752edaa35123e0941
This commit is contained in:
Rex-BC Chen 2021-12-02 14:03:44 +08:00 • committed by Rex-BC Chen
parent 7d00e72a39
commit e46e9df0d0
6 changed files with 178 additions and 1 deletions
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98
plat/mediatek/mt8186/drivers/dfd/plat_dfd.c Normal file
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@ -0,0 +1,98 @@
/*
* Copyright (c) 2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
static bool dfd_enabled;
static uint64_t dfd_base_addr;
static uint64_t dfd_chain_length;
static uint64_t dfd_cache_dump;
static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
uint64_t cache_dump)
{
mmio_write_32(MCUSYS_DFD_MAP, base_addr >> 24);
mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_0);
sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2)));
mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13));
mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3));
mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20)));
mmio_write_32(DFD_INTERNAL_PWR_ON, (BIT(0) | BIT(1) | BIT(3)));
mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0);
mmio_write_32(DFD_INTERNAL_TEST_SO_0, DFD_INTERNAL_TEST_SO_0_VAL);
mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 1);
mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_VAL);
mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL);
sync_writel(DFD_V30_CTL, 1);
mmio_write_32(DFD_V30_BASE_ADDR, (base_addr & 0xFFF00000));
/* setup global variables for suspend and resume */
dfd_enabled = true;
dfd_base_addr = base_addr;
dfd_chain_length = chain_length;
dfd_cache_dump = cache_dump;
if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_1);
sync_writel(DFD_V35_ENALBE, 1);
sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL);
sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
if (cache_dump & DFD_PARITY_ERR_TRIGGER) {
sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL);
mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4));
}
}
dsbsy();
}
void dfd_resume(void)
{
if (dfd_enabled == true) {
dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
}
}
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3)
{
uint64_t ret = 0L;
switch (arg0) {
case PLAT_MTK_DFD_SETUP_MAGIC:
INFO("[%s] DFD setup call from kernel\n", __func__);
dfd_setup(arg1, arg2, arg3);
break;
case PLAT_MTK_DFD_READ_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
ret = mmio_read_32(MISC1_CFG_BASE + arg1);
}
break;
case PLAT_MTK_DFD_WRITE_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
sync_writel(MISC1_CFG_BASE + arg1, arg2);
}
break;
default:
ret = MTK_SIP_E_INVALID_PARAM;
break;
}
return ret;
}

64
plat/mediatek/mt8186/drivers/dfd/plat_dfd.h Normal file
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@ -0,0 +1,64 @@
/*
* Copyright (c) 2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_DFD_H
#define PLAT_DFD_H
#include <arch_helpers.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
dsbsy(); \
} while (0)
#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
#define MCU_BIU_BASE (MCUCFG_BASE)
#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040)
#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xA0A8)
#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xA0AC)
#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xA0B0)
#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xA0C0)
#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xA0C4)
#define DFD_CACHE_DUMP_ENABLE (1U)
#define DFD_PARITY_ERR_TRIGGER (2U)
#define MCUSYS_DFD_MAP (0x10001390)
#define WDT_DEBUG_CTL (0x10007048)
#define WDT_DEBUG_CTL_VAL_0 (0x950603A0)
#define DFD_INTERNAL_TEST_SO_0_VAL (0x3B)
#define DFD_TEST_SI_0_VAL (0x108)
#define DFD_TEST_SI_1_VAL (0x20200000)
#define WDT_DEBUG_CTL_VAL_1 (0x95063E80)
#define DFD_V35_TAP_NUMBER_VAL (0xA)
#define DFD_V35_TAP_EN_VAL (0x3FF)
#define DFD_V35_SEQ0_0_VAL (0x63668820)
#define DFD_HW_TRIGGER_MASK_VAL (0xC)
void dfd_resume(void);
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3);
#endif /* PLAT_DFD_H */

6
plat/mediatek/mt8186/include/plat_sip_calls.h
View file

@ -10,6 +10,10 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
#define MTK_PLAT_SIP_NUM_CALLS 0
#define MTK_PLAT_SIP_NUM_CALLS (2)
/* DFD */
#define MTK_SIP_KERNEL_DFD_AARCH32 (0x82000205)
#define MTK_SIP_KERNEL_DFD_AARCH64 (0xC2000205)
#endif /* PLAT_SIP_CALLS_H */

3
plat/mediatek/mt8186/plat_pm.c
View file

@ -13,6 +13,7 @@
#include <mt_gic_v3.h>
#include <mtspmc.h>
#include <plat/common/platform.h>
#include <plat_dfd.h>
#include <plat_mtk_lpm.h>
#include <plat_params.h>
#include <plat_pm.h>
@ -164,6 +165,8 @@ static void plat_mcusys_pwron_common(unsigned int cpu,
mt_gic_distif_restore();
gic_sgi_restore_all();
dfd_resume();
(void)plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_on_finished, cpu, state);
}

6
plat/mediatek/mt8186/plat_sip_calls.c
View file

@ -8,6 +8,7 @@
#include <common/runtime_svc.h>
#include <mt_spm_vcorefs.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
#include "plat_sip_calls.h"
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
@ -27,6 +28,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
SMC_RET2(handle, ret, x4);
break;
case MTK_SIP_KERNEL_DFD_AARCH32:
case MTK_SIP_KERNEL_DFD_AARCH64:
ret = dfd_smc_dispatcher(x1, x2, x3, x4);
SMC_RET1(handle, ret);
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;

2
plat/mediatek/mt8186/platform.mk
View file

@ -15,6 +15,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/dcm/ \
-I${MTK_PLAT_SOC}/drivers/dfd/ \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
@ -58,6 +59,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \