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fdts: a5ds: Fix for the system timer issue.

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A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.

Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
This commit is contained in:
lakshmi Kailasanathan 2020-04-17 12:52:19 +01:00
parent 6428938ff4
commit e3c152d115
1 changed files with 1 additions and 1 deletions
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2
fdts/a5ds.dts
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@ -128,7 +128,7 @@
#size-cells = <1>;
ranges;
reg = <0x1a040000 0x1000>;
clock-frequency = <50000000>;
clock-frequency = <7500000>;
frame@1a050000 {
frame-number = <0>;