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fix(nxp-drivers): ddr: corrects mapping of HNFs nodes
Corrects mapping of HNFs nodes with SNFs nodes based on their proximity in CCN508 ring when disabling unused ddr controller. When DDRC 2 disabled and DDR 1 is active the mapping is 0x3/3/8/8/8/8/3/3. When DDRC 1 is disabled and DDR2 is active the mapping is 0x 18/18/13/13/13/13/18/18 . Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by: JaiPrakash Singh <JaiPrakash.singh@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I6ec1e02f8ad7e8bb8628913625ff5313a054dcc6
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1 changed files with 19 additions and 6 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2021 NXP
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* Copyright 2021-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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@ -33,8 +33,10 @@
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#define CCN_HN_F_SAM_NODEID_DDR0 0x4
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#define CCN_HN_F_SAM_NODEID_DDR1 0xe
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#elif defined(NXP_HAS_CCN508)
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#define CCN_HN_F_SAM_NODEID_DDR0 0x8
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#define CCN_HN_F_SAM_NODEID_DDR1 0x18
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#define CCN_HN_F_SAM_NODEID_DDR0_0 0x3
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#define CCN_HN_F_SAM_NODEID_DDR0_1 0x8
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#define CCN_HN_F_SAM_NODEID_DDR1_0 0x13
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#define CCN_HN_F_SAM_NODEID_DDR1_1 0x18
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#endif
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unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num)
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@ -166,10 +168,21 @@ int disable_unused_ddrc(struct ddr_info *priv,
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for (i = 0; i < num_hnf_nodes; i++) {
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val = mmio_read_64((uintptr_t)hnf_sam_ctrl);
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#ifdef NXP_HAS_CCN504
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nodeid = disable_ddrc == 1 ? CCN_HN_F_SAM_NODEID_DDR1 :
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(disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 :
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(i < 4 ? CCN_HN_F_SAM_NODEID_DDR0
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: CCN_HN_F_SAM_NODEID_DDR1));
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(disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 :
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0x0); /*Failure condition. never hit */
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#elif defined(NXP_HAS_CCN508)
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if (disable_ddrc == 1) {
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nodeid = (i < 2 || i >= 6) ? CCN_HN_F_SAM_NODEID_DDR1_1 :
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CCN_HN_F_SAM_NODEID_DDR1_0;
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} else if (disable_ddrc == 2) {
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nodeid = (i < 2 || i >= 6) ? CCN_HN_F_SAM_NODEID_DDR0_0 :
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CCN_HN_F_SAM_NODEID_DDR0_1;
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} else {
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nodeid = 0; /* Failure condition. never hit */
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}
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#endif
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if (nodeid != (val & CCN_HN_F_SAM_NODEID_MASK)) {
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debug("Setting HN-F node %d\n", i);
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debug("nodeid = 0x%x\n", nodeid);
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