From e365479d0d89999f815ea71b1511ff7952b479e2 Mon Sep 17 00:00:00 2001
From: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Date: Tue, 23 Apr 2024 10:04:44 +0100
Subject: [PATCH] feat(tc): bind DPU SMMU on TC4

TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is
used as the DPU SMMU instead of the existing SMMU used for both the GPU
and DPU. Update the devicetree to reflect this.

Note that the streamID values have also changes for this new SMMU. This
is because TC4 also updates the new SMMU to use a different streamID for
each DPU port - these must all be added to the device tree.

Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
 fdts/tc4.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 8b21be1d9..135d30a22 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -50,6 +50,15 @@
 		status = "okay";
 	};
 
+	smmu_700_dpu: iommu@4002a00000 {
+		status = "okay";
+	};
+
+	dp0: display@DPU_ADDR {
+		iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
+			 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
+	};
+
 	gpu: gpu@2d000000 {
 		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
 		interrupt-names = "IRQAW";