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fix(cadence): update console flush uart driver
The implementation of code changes manages the transmit FIFO (TxFIFO) in the UART driver. The added code snippet includes a sequence of instructions that ensures efficient handling of data transmission and synchronization with the host software. The code first checks the TxFIFO empty flag to determine whether there is data available for transmission. If the TxFIFO is not empty, the code waits until it becomes empty, ensuring that the transmit operation is synchronized with the availability of data. Subsequently, the code monitors the transmit operation's activity status. It waits until the transmit operation becomes inactive, indicating the completion of the previous transmission. This synchronization step ensures that new data can be added to the TxFIFO without causing any loss of transmission time. Update console_flush() function, the function waits for the Transmitter FIFO to empty and checks the transmitter's active state. If the transmitter is in an active state, it means it is currently shifting out a character. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Change-Id: I9d6c05bdfb9270924b40bf1f6ecb5fe541a2242e
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2 changed files with 9 additions and 1 deletions
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@ -197,7 +197,14 @@ func console_cdns_core_flush
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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/* Placeholder */
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/* Loop until the transmit FIFO is empty */
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check_txfifo_empty:
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ldr w2, [x0, #R_UART_SR]
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tbz w2, #UART_SR_INTR_TEMPTY_BIT, check_txfifo_empty
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/* Wait until the Transmit is Inactive */
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check_tx_inactive_state:
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ldr w2, [x0, #R_UART_SR]
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tbnz w2, #UART_SR_INTR_TACTIVE_BIT, check_tx_inactive_state
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ret
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endfunc console_cdns_core_flush
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@ -22,6 +22,7 @@
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#define UART_SR_INTR_REMPTY_BIT 1
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#define UART_SR_INTR_TFUL_BIT 4
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#define UART_SR_INTR_TEMPTY_BIT 3
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#define UART_SR_INTR_TACTIVE_BIT 11
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#define R_UART_TX 0x30
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#define R_UART_RX 0x30
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