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Merge changes from topic "feat_amu_rework" into integration

Browse source 
* changes:
  refactor(amu): use new AMU feature check routines
  refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1
This commit is contained in:
Manish Pandey 2023-03-28 12:24:59 +02:00 • committed by TrustedFirmware Code Review
commit e24e42c605
30 changed files with 123 additions and 148 deletions
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6
Makefile
View file

@ -1092,7 +1092,6 @@ $(eval $(call assert_booleans,\
DISABLE_MTPMU \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
ENABLE_AMU \
ENABLE_AMU_AUXILIARY_COUNTERS \
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
@ -1172,7 +1171,7 @@ $(eval $(call assert_numerics,\
ENABLE_TRBE_FOR_NS \
ENABLE_BTI \
ENABLE_PAUTH \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_AMU \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_CSV2_2 \
ENABLE_FEAT_DIT \
@ -1229,7 +1228,7 @@ $(eval $(call add_defines,\
CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
DISABLE_MTPMU \
ENABLE_AMU \
ENABLE_FEAT_AMU \
ENABLE_AMU_AUXILIARY_COUNTERS \
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
@ -1310,7 +1309,6 @@ $(eval $(call add_defines,\
ENABLE_MPMM \
ENABLE_MPMM_FCONF \
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
ENABLE_FEAT_AMUv1p1 \

2
bl31/bl31.mk
View file

@ -91,7 +91,7 @@ ifneq (${ENABLE_SPE_FOR_NS},0)
BL31_SOURCES += lib/extensions/spe/spe.c
endif
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL31_SOURCES += ${AMU_SOURCES}
endif

2
bl32/sp_min/sp_min.mk
View file

@ -28,7 +28,7 @@ ifeq (${ENABLE_PMF}, 1)
BL32_SOURCES += lib/pmf/pmf_main.c
endif
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL32_SOURCES += ${AMU_SOURCES}
endif

15
common/feat_detect.c
View file

@ -112,16 +112,6 @@ static void read_feat_bti(void)
#endif
}
/***********************************************
* Feature : FEAT_AMUv1p1 (AMU Extensions v1.1)
**********************************************/
static void read_feat_amuv1p1(void)
{
#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_6_feat_amuv1p1_present(), "AMUv1p1");
#endif
}
/**************************************************
* Feature : FEAT_RME (Realm Management Extension)
*************************************************/
@ -187,7 +177,7 @@ void detect_arch_features(void)
/* v8.4 features */
read_feat_dit();
check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(),
check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
"AMUv1", 1, 2);
check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
"MPAM", 1, 17);
@ -205,7 +195,8 @@ void detect_arch_features(void)
read_feat_rng_trap();
/* v8.6 features */
read_feat_amuv1p1();
check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
"AMUv1p1", 2, 2);
check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),

6
docs/components/activity-monitors.rst
View file

@ -6,9 +6,9 @@ extension. This extension describes the architecture for the Activity Monitor
Unit (|AMU|), an optional non-invasive component for monitoring core events
through a set of 64-bit counters.
When the ``ENABLE_AMU=1`` build option is provided, Trusted Firmware-A sets up
the |AMU| prior to its exit from EL3, and will save and restore architected
|AMU| counters as necessary upon suspend and resume.
When the ``ENABLE_FEAT_AMU=1`` build option is provided, Trusted Firmware-A
sets up the |AMU| prior to its exit from EL3, and will save and restore
architected |AMU| counters as necessary upon suspend and resume.
.. _Activity Monitor Auxiliary Counters:

18
docs/getting_started/build-options.rst
View file

@ -230,11 +230,6 @@ Common build options
payload. Please refer to the "Booting an EL3 payload" section for more
details.
- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
This is an optional architectural feature available on v8.4 onwards. Some
v8.2 implementations also implement an AMU and this option can be used to
enable this feature on those systems as well. Default is 0.
- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
(also known as group 1 counters). These are implementation-defined counters,
and as such require additional platform configuration. Default is 0.
@ -261,13 +256,12 @@ Common build options
builds, but this behaviour can be overridden in each platform's Makefile or
in the build command line.
- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2
(Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2
to EL3 context save/restore operations. This flag can take the values 0 to 2,
to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature
available on v8.4 and onwards and must be set to either 1 or 2 alongside
``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register.
Default value is ``0``.
- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
extensions. This flag can take the values 0 to 2, to align with the
``FEATURE_DETECTION`` mechanism. This is an optional architectural feature
available on v8.4 onwards. Some v8.2 implementations also implement an AMU
and this option can be used to enable this feature on those systems as well.
This flag can take the values 0 to 2, the default is 0.
- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6

31
include/arch/aarch32/arch_features.h
View file

@ -25,6 +25,37 @@ static inline bool is_armv8_2_ttcnp_present(void)
return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
}
static unsigned int read_feat_amu_id_field(void)
{
return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_AMU);
}
static inline bool is_feat_amu_supported(void)
{
if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_PFR0_AMU_V1;
}
static inline bool is_feat_amuv1p1_supported(void)
{
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_PFR0_AMU_V1P1;
}
static inline unsigned int read_feat_trf_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT);

14
include/arch/aarch64/arch_features.h
View file

@ -244,19 +244,27 @@ static unsigned int read_feat_amu_id_field(void)
static inline bool is_feat_amu_supported(void)
{
if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) {
if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) {
if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
}
static inline bool is_armv8_6_feat_amuv1p1_present(void)
static inline bool is_feat_amuv1p1_supported(void)
{
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
}

12
include/lib/extensions/amu.h
View file

@ -14,11 +14,23 @@
#include <platform_def.h>
#if ENABLE_FEAT_AMU
#if __aarch64__
void amu_enable(bool el2_unused, cpu_context_t *ctx);
#else
void amu_enable(bool el2_unused);
#endif
#else
#if __aarch64__
static inline void amu_enable(bool el2_unused, cpu_context_t *ctx)
{
}
#else
static inline void amu_enable(bool el2_unused)
{
}
#endif
#endif
#if ENABLE_AMU_AUXILIARY_COUNTERS
/*

2
lib/cpus/aarch64/cortex_a75.S
View file

@ -121,7 +121,7 @@ func cortex_a75_reset_func
bl errata_dsu_936184_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT

2
lib/cpus/aarch64/cortex_a78.S
View file

@ -483,7 +483,7 @@ func cortex_a78_reset_func
bl errata_a78_2779479_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT

2
lib/cpus/aarch64/cortex_a78_ae.S
View file

@ -214,7 +214,7 @@ func cortex_a78_ae_reset_func
bl errata_a78_ae_2395408_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT

2
lib/cpus/aarch64/neoverse_n1.S
View file

@ -585,7 +585,7 @@ func neoverse_n1_reset_func
bl errata_n1_1946160_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT

2
lib/cpus/aarch64/neoverse_n2.S
View file

@ -545,7 +545,7 @@ func neoverse_n2_reset_func
bl errata_n2_2388450_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, cptr_el3
orr x0, x0, #TAM_BIT

2
lib/cpus/aarch64/rainier.S
View file

@ -94,7 +94,7 @@ func rainier_reset_func
bl errata_n1_1868343_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #RAINIER_ACTLR_AMEN_BIT

6
lib/el3_runtime/aarch32/context_mgmt.c
View file

@ -136,9 +136,9 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
static void enable_extensions_nonsecure(bool el2_unused)
{
#if IMAGE_BL32
#if ENABLE_AMU
amu_enable(el2_unused);
#endif
if (is_feat_amu_supported()) {
amu_enable(el2_unused);
}
if (is_feat_sys_reg_trace_supported()) {
sys_reg_trace_enable();

6
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -485,9 +485,9 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
spe_enable(el2_unused);
}
#if ENABLE_AMU
amu_enable(el2_unused, ctx);
#endif
if (is_feat_amu_supported()) {
amu_enable(el2_unused, ctx);
}
#if ENABLE_SME_FOR_NS
/* Enable SME, SVE, and FPU/SIMD for non-secure world. */

44
lib/extensions/amu/aarch32/amu.c
View file

@ -10,6 +10,7 @@
#include "../amu_private.h"
#include <arch.h>
#include <arch_features.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/el3_runtime/pubsub_events.h>
@ -39,12 +40,6 @@ CASSERT((sizeof(amu_ctxs_[0].group1_enable) * CHAR_BIT) <= AMU_GROUP1_MAX_COUNTE
amu_ctx_group1_enable_cannot_represent_all_group1_counters);
#endif
static inline __unused uint32_t read_id_pfr0_amu(void)
{
return (read_id_pfr0() >> ID_PFR0_AMU_SHIFT) &
ID_PFR0_AMU_MASK;
}
static inline __unused void write_hcptr_tam(uint32_t value)
{
write_hcptr((read_hcptr() & ~TAM_BIT) |
@ -129,11 +124,6 @@ static inline __unused void write_amcntenclr1_px(uint32_t px)
write_amcntenclr1(value);
}
static __unused bool amu_supported(void)
{
return read_id_pfr0_amu() >= ID_PFR0_AMU_V1;
}
#if ENABLE_AMU_AUXILIARY_COUNTERS
static __unused bool amu_group1_supported(void)
{
@ -147,23 +137,12 @@ static __unused bool amu_group1_supported(void)
*/
void amu_enable(bool el2_unused)
{
uint32_t id_pfr0_amu; /* AMU version */
uint32_t amcfgr_ncg; /* Number of counter groups */
uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
uint32_t amcntenset0_px = 0x0; /* Group 0 enable mask */
uint32_t amcntenset1_px = 0x0; /* Group 1 enable mask */
id_pfr0_amu = read_id_pfr0_amu();
if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) {
/*
* If the AMU is unsupported, nothing needs to be done.
*/
return;
}
if (el2_unused) {
/*
* HCPTR.TAM: Set to zero so any accesses to the Activity
@ -221,8 +200,8 @@ void amu_enable(bool el2_unused)
#endif
}
/* Initialize FEAT_AMUv1p1 features if present. */
if (id_pfr0_amu < ID_PFR0_AMU_V1P1) {
/* Bail out if FEAT_AMUv1p1 features are not present. */
if (!is_feat_amuv1p1_supported()) {
return;
}
@ -244,7 +223,7 @@ void amu_enable(bool el2_unused)
/* Read the group 0 counter identified by the given `idx`. */
static uint64_t amu_group0_cnt_read(unsigned int idx)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(idx < read_amcgcr_cg0nc());
return amu_group0_cnt_read_internal(idx);
@ -253,7 +232,7 @@ static uint64_t amu_group0_cnt_read(unsigned int idx)
/* Write the group 0 counter identified by the given `idx` with `val` */
static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(idx < read_amcgcr_cg0nc());
amu_group0_cnt_write_internal(idx, val);
@ -264,7 +243,7 @@ static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
/* Read the group 1 counter identified by the given `idx` */
static uint64_t amu_group1_cnt_read(unsigned int idx)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_cg1nc());
@ -274,7 +253,7 @@ static uint64_t amu_group1_cnt_read(unsigned int idx)
/* Write the group 1 counter identified by the given `idx` with `val` */
static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_cg1nc());
@ -290,7 +269,6 @@ static void *amu_context_save(const void *arg)
unsigned int core_pos;
struct amu_ctx *ctx;
uint32_t id_pfr0_amu; /* AMU version */
uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
#if ENABLE_AMU_AUXILIARY_COUNTERS
@ -298,8 +276,7 @@ static void *amu_context_save(const void *arg)
uint32_t amcgcr_cg1nc; /* Number of group 1 counters */
#endif
id_pfr0_amu = read_id_pfr0_amu();
if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) {
if (!is_feat_amu_supported()) {
return (void *)0;
}
@ -353,8 +330,6 @@ static void *amu_context_restore(const void *arg)
unsigned int core_pos;
struct amu_ctx *ctx;
uint32_t id_pfr0_amu; /* AMU version */
uint32_t amcfgr_ncg; /* Number of counter groups */
uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
@ -362,8 +337,7 @@ static void *amu_context_restore(const void *arg)
uint32_t amcgcr_cg1nc; /* Number of group 1 counters */
#endif
id_pfr0_amu = read_id_pfr0_amu();
if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) {
if (!is_feat_amu_supported()) {
return (void *)0;
}

68
lib/extensions/amu/aarch64/amu.c
View file

@ -57,12 +57,6 @@ CASSERT((sizeof(amu_ctxs_[0].group1_enable) * CHAR_BIT) <= AMU_GROUP1_MAX_COUNTE
amu_ctx_group1_enable_cannot_represent_all_group1_counters);
#endif
static inline __unused uint64_t read_id_aa64pfr0_el1_amu(void)
{
return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
ID_AA64PFR0_AMU_MASK;
}
static inline __unused uint64_t read_hcr_el2_amvoffen(void)
{
return (read_hcr_el2() & HCR_AMVOFFEN_BIT) >>
@ -183,16 +177,6 @@ static inline __unused void write_amcntenclr1_el0_px(uint64_t px)
write_amcntenclr1_el0(value);
}
static __unused bool amu_supported(void)
{
return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1;
}
static __unused bool amu_v1p1_supported(void)
{
return read_id_aa64pfr0_el1_amu() >= ID_AA64PFR0_AMU_V1P1;
}
#if ENABLE_AMU_AUXILIARY_COUNTERS
static __unused bool amu_group1_supported(void)
{
@ -206,23 +190,12 @@ static __unused bool amu_group1_supported(void)
*/
void amu_enable(bool el2_unused, cpu_context_t *ctx)
{
uint64_t id_aa64pfr0_el1_amu; /* AMU version */
uint64_t amcfgr_el0_ncg; /* Number of counter groups */
uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
uint64_t amcntenset0_el0_px = 0x0; /* Group 0 enable mask */
uint64_t amcntenset1_el0_px = 0x0; /* Group 1 enable mask */
id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
/*
* If the AMU is unsupported, nothing needs to be done.
*/
return;
}
if (el2_unused) {
/*
* CPTR_EL2.TAM: Set to zero so any accesses to the Activity
@ -288,7 +261,7 @@ void amu_enable(bool el2_unused, cpu_context_t *ctx)
}
/* Initialize FEAT_AMUv1p1 features if present. */
if (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) {
if (is_feat_amuv1p1_supported()) {
if (el2_unused) {
/*
* Make sure virtual offsets are disabled if EL2 not
@ -327,7 +300,7 @@ void amu_enable(bool el2_unused, cpu_context_t *ctx)
/* Read the group 0 counter identified by the given `idx`. */
static uint64_t amu_group0_cnt_read(unsigned int idx)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(idx < read_amcgcr_el0_cg0nc());
return amu_group0_cnt_read_internal(idx);
@ -336,7 +309,7 @@ static uint64_t amu_group0_cnt_read(unsigned int idx)
/* Write the group 0 counter identified by the given `idx` with `val` */
static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(idx < read_amcgcr_el0_cg0nc());
amu_group0_cnt_write_internal(idx, val);
@ -376,7 +349,7 @@ static bool amu_group0_voffset_supported(uint64_t idx)
*/
static uint64_t amu_group0_voffset_read(unsigned int idx)
{
assert(amu_v1p1_supported());
assert(is_feat_amuv1p1_supported());
assert(idx < read_amcgcr_el0_cg0nc());
assert(idx != 1U);
@ -391,7 +364,7 @@ static uint64_t amu_group0_voffset_read(unsigned int idx)
*/
static void amu_group0_voffset_write(unsigned int idx, uint64_t val)
{
assert(amu_v1p1_supported());
assert(is_feat_amuv1p1_supported());
assert(idx < read_amcgcr_el0_cg0nc());
assert(idx != 1U);
@ -403,7 +376,7 @@ static void amu_group0_voffset_write(unsigned int idx, uint64_t val)
/* Read the group 1 counter identified by the given `idx` */
static uint64_t amu_group1_cnt_read(unsigned int idx)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_el0_cg1nc());
@ -413,7 +386,7 @@ static uint64_t amu_group1_cnt_read(unsigned int idx)
/* Write the group 1 counter identified by the given `idx` with `val` */
static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
{
assert(amu_supported());
assert(is_feat_amu_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_el0_cg1nc());
@ -428,7 +401,7 @@ static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
*/
static uint64_t amu_group1_voffset_read(unsigned int idx)
{
assert(amu_v1p1_supported());
assert(is_feat_amuv1p1_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_el0_cg1nc());
assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U);
@ -443,7 +416,7 @@ static uint64_t amu_group1_voffset_read(unsigned int idx)
*/
static void amu_group1_voffset_write(unsigned int idx, uint64_t val)
{
assert(amu_v1p1_supported());
assert(is_feat_amuv1p1_supported());
assert(amu_group1_supported());
assert(idx < read_amcgcr_el0_cg1nc());
assert((read_amcg1idr_el0_voff() & (UINT64_C(1) << idx)) != 0U);
@ -460,8 +433,7 @@ static void *amu_context_save(const void *arg)
unsigned int core_pos;
struct amu_ctx *ctx;
uint64_t id_aa64pfr0_el1_amu; /* AMU version */
uint64_t hcr_el2_amvoffen; /* AMU virtual offsets enabled */
uint64_t hcr_el2_amvoffen = 0; /* AMU virtual offsets enabled */
uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
#if ENABLE_AMU_AUXILIARY_COUNTERS
@ -470,8 +442,7 @@ static void *amu_context_save(const void *arg)
uint64_t amcgcr_el0_cg1nc; /* Number of group 1 counters */
#endif
id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
if (!is_feat_amu_supported()) {
return (void *)0;
}
@ -479,8 +450,9 @@ static void *amu_context_save(const void *arg)
ctx = &amu_ctxs_[core_pos];
amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc();
hcr_el2_amvoffen = (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) ?
read_hcr_el2_amvoffen() : 0U;
if (is_feat_amuv1p1_supported()) {
hcr_el2_amvoffen = read_hcr_el2_amvoffen();
}
#if ENABLE_AMU_AUXILIARY_COUNTERS
amcfgr_el0_ncg = read_amcfgr_el0_ncg();
@ -552,9 +524,7 @@ static void *amu_context_restore(const void *arg)
unsigned int core_pos;
struct amu_ctx *ctx;
uint64_t id_aa64pfr0_el1_amu; /* AMU version */
uint64_t hcr_el2_amvoffen; /* AMU virtual offsets enabled */
uint64_t hcr_el2_amvoffen = 0; /* AMU virtual offsets enabled */
uint64_t amcfgr_el0_ncg; /* Number of counter groups */
uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */
@ -564,8 +534,7 @@ static void *amu_context_restore(const void *arg)
uint64_t amcg1idr_el0_voff; /* Auxiliary counters with virtual offsets */
#endif
id_aa64pfr0_el1_amu = read_id_aa64pfr0_el1_amu();
if (id_aa64pfr0_el1_amu == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
if (!is_feat_amu_supported()) {
return (void *)0;
}
@ -575,8 +544,9 @@ static void *amu_context_restore(const void *arg)
amcfgr_el0_ncg = read_amcfgr_el0_ncg();
amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc();
hcr_el2_amvoffen = (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) ?
read_hcr_el2_amvoffen() : 0U;
if (is_feat_amuv1p1_supported()) {
hcr_el2_amvoffen = read_hcr_el2_amvoffen();
}
#if ENABLE_AMU_AUXILIARY_COUNTERS
amcgcr_el0_cg1nc = (amcfgr_el0_ncg > 0U) ? read_amcgcr_el0_cg1nc() : 0U;

4
lib/extensions/amu/amu.mk
View file

@ -10,8 +10,8 @@ AMU_SOURCES := lib/extensions/amu/${ARCH}/amu.c \
lib/extensions/amu/${ARCH}/amu_helpers.S
ifneq (${ENABLE_AMU_AUXILIARY_COUNTERS},0)
ifeq (${ENABLE_AMU},0)
$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENABLE_AMU`))
ifeq (${ENABLE_FEAT_AMU},0)
$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENABLE_FEAT_AMU`))
endif
endif

5
make_helpers/defaults.mk
View file

@ -133,9 +133,6 @@ ENABLE_BTI := 0
# Use BRANCH_PROTECTION to enable PAUTH.
ENABLE_PAUTH := 0
# Flag to enable access to the HAFGRTR_EL2 register
ENABLE_FEAT_AMUv1 := 0
# Flag to enable AMUv1p1 extension.
ENABLE_FEAT_AMUv1p1 := 0
@ -367,7 +364,7 @@ endif
# enabled at ELX.
CTX_INCLUDE_MTE_REGS := 0
ENABLE_AMU := 0
ENABLE_FEAT_AMU := 0
ENABLE_AMU_AUXILIARY_COUNTERS := 0
ENABLE_AMU_FCONF := 0
AMU_RESTRICT_COUNTERS := 0

2
plat/arm/board/arm_fpga/platform.mk
View file

@ -33,7 +33,7 @@ $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
FPGA_PRELOADED_CMD_LINE := 0x1000
$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0

5
plat/arm/board/fvp/platform.mk
View file

@ -319,12 +319,13 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
endif
# Enable Activity Monitor Unit extensions by default
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
ENABLE_FEAT_AMUv1p1 := 2
# Enable dynamic mitigation support by default
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
lib/cpus/aarch64/cpuamu_helpers.S

2
plat/arm/board/fvp_r/platform.mk
View file

@ -69,7 +69,7 @@ FVP_R_BL_COMMON_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
# Enable Activity Monitor Unit extensions by default
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
ifneq (${ENABLE_STACK_PROTECTOR},0)
FVP_R_BL_COMMON_SOURCES += plat/arm/board/fvp_r/fvp_r_stack_protector.c

2
plat/arm/board/rdn2/platform.mk
View file

@ -87,4 +87,4 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1

2
plat/arm/board/rdv1/platform.mk
View file

@ -57,7 +57,7 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \

2
plat/arm/board/rdv1mc/platform.mk
View file

@ -68,7 +68,7 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \

2
plat/arm/board/tc/platform.mk
View file

@ -163,7 +163,7 @@ override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_NS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
override ENABLE_AMU_AUXILIARY_COUNTERS := 1
override ENABLE_AMU_FCONF := 1

2
plat/mediatek/common/common_config.mk
View file

@ -19,7 +19,7 @@ GIC_DEBUG := 0
ENABLE_STACK_PROTECTOR := strong
# AMU, Kernel will access amuserenr_el0 if PE supported
# Firmware _must_ implement AMU support
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
VENDOR_EXTEND_PUBEVENT_ENABLE := 1
# MTK define options

1
plat/qti/msm8916/platform.mk
View file

@ -43,7 +43,6 @@ SEPARATE_CODE_AND_RODATA := 1
WARMBOOT_ENABLE_DCACHE_EARLY := 1
# Disable features unsupported in ARMv8.0
ENABLE_AMU := 0
ENABLE_SPE_FOR_NS := 0
ENABLE_SVE_FOR_NS := 0