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fdts: add device tree sources for morello platform
Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
This commit is contained in:
Manoj Kumar
Chandni Cherukuri
parent
2b357c3159
commit
e1cbcf965f
2 changed files with 239 additions and 0 deletions
133
fdts/morello-fvp.dts
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133
fdts/morello-fvp.dts
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "morello.dtsi"
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/ {
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chosen {
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stdout-path = "soc_uart0:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-firmware@ff000000 {
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reg = <0 0xff000000 0 0x01000000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu1@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu2@10000 {
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu3@10100 {
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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};
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x80000000>;
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};
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memory@8080000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x8080000000-0x83ffffffff] */
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reg = <0x00000080 0x80000000 0x1 0x80000000>;
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};
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virtio_block@1c170000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c170000 0x0 0x200>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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};
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ethernet@1d100000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x1d100000 0x0 0x10000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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kmi@1c150000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c150000 0x0 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c160000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c160000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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};
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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};
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&gic {
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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106
fdts/morello.dtsi
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106
fdts/morello.dtsi
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@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "arm,morello";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-600", "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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mailbox: mhu@45000000 {
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compatible = "arm,mhu-doorbell", "arm,primecell";
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reg = <0x0 0x45000000 0x0 0x1000>;
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interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhu_lpri_rx",
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"mhu_hpri_rx";
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#mbox-cells = <2>;
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mbox-name = "ARM-MHU";
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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};
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sram: sram@45200000 {
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compatible = "mmio-sram";
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reg = <0x0 0x45200000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x45200000 0x8000>;
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cpu_scp_hpri0: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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cpu_scp_hpri1: scp-shmem@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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soc_uart0: uart@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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};
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