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fix(errata): workaround for Cortex X2 erratum 2058056

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Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)

However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
This commit is contained in:
johpow01 2021-12-03 11:27:33 -06:00
parent 34ee76dbdf
commit e16045de50
4 changed files with 56 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -447,6 +447,10 @@ For Cortex-X2, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
it is still open.
- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
it is still open.
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.

9
include/lib/cpus/aarch64/cortex_x2.h
View file

@ -14,6 +14,15 @@
******************************************************************************/
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Extended Control register 2 specific definitions
******************************************************************************/
#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/

35
lib/cpus/aarch64/cortex_x2.S
View file

@ -55,6 +55,35 @@ func check_errata_2002765
b cpu_rev_var_ls
endfunc check_errata_2002765
/* --------------------------------------------------
* Errata Workaround for Cortex X2 Errata #2058056.
* This applies to revisions r0p0, r1p0, and r2p0 and
* is open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_x2_2058056_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2058056
cbz x0, 1f
mrs x1, CORTEX_X2_CPUECTLR2_EL1
mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
msr CORTEX_X2_CPUECTLR2_EL1, x1
1:
ret x17
endfunc errata_cortex_x2_2058056_wa
func check_errata_2058056
/* Applies to r0p0 - r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2058056
/* --------------------------------------------------
* Errata Workaround for Cortex X2 Errata #2083908.
* This applies to revision r2p0 and is open.
@ -115,6 +144,7 @@ func cortex_x2_errata_report
* checking functions of each errata.
*/
report_errata ERRATA_X2_2002765, cortex_x2, 2002765
report_errata ERRATA_X2_2058056, cortex_x2, 2058056
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
ldp x8, x30, [sp], #16
@ -138,6 +168,11 @@ func cortex_x2_reset_func
bl errata_cortex_x2_2002765_wa
#endif
#if ERRATA_X2_2058056
mov x0, x18
bl errata_cortex_x2_2058056_wa
#endif
#if ERRATA_X2_2083908
mov x0, x18
bl errata_cortex_x2_2083908_wa

8
lib/cpus/cpu-ops.mk
View file

@ -499,6 +499,10 @@ ERRATA_A710_2017096 ?=0
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2002765 ?=0
# Flag to apply erratum 2058056 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2058056 ?=0
# Flag to apply erratum 2083908 workaround during reset. This erratum applies
# to revision r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2083908 ?=0
@ -932,6 +936,10 @@ $(eval $(call add_define,ERRATA_A710_2017096))
$(eval $(call assert_boolean,ERRATA_X2_2002765))
$(eval $(call add_define,ERRATA_X2_2002765))
# Process ERRATA_X2_2058056 flag
$(eval $(call assert_boolean,ERRATA_X2_2058056))
$(eval $(call add_define,ERRATA_X2_2058056))
# Process ERRATA_X2_2083908 flag
$(eval $(call assert_boolean,ERRATA_X2_2083908))
$(eval $(call add_define,ERRATA_X2_2083908))