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Merge changes from topic "hm/errata-fw" into integration

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* changes:
  refactor(cpus): add Cortex-A17 errata framework information
  fix(fvp): resolve broken workaround reference
This commit is contained in:
Bipin Ravi 2023-07-28 00:21:42 +02:00 • committed by TrustedFirmware Code Review
commit e070eadbb2
2 changed files with 11 additions and 26 deletions
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31
lib/cpus/aarch32/cortex_a17.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -63,6 +63,8 @@ func check_errata_852421
b cpu_rev_var_ls b cpu_rev_var_ls
endfunc check_errata_852421 endfunc check_errata_852421
add_erratum_entry cortex_a17, ERRATUM(852421), ERRATA_A17_852421
/* ---------------------------------------------------- /* ----------------------------------------------------
* Errata Workaround for Cortex A17 Errata #852423. * Errata Workaround for Cortex A17 Errata #852423.
* This applies only to revision <= r1p2 of Cortex A17. * This applies only to revision <= r1p2 of Cortex A17.
@ -91,6 +93,8 @@ func check_errata_852423
b cpu_rev_var_ls b cpu_rev_var_ls
endfunc check_errata_852423 endfunc check_errata_852423
add_erratum_entry cortex_a17, ERRATUM(852423), ERRATA_A17_852423
func check_errata_cve_2017_5715 func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715 #if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES mov r0, #ERRATA_APPLIES
@ -100,28 +104,9 @@ func check_errata_cve_2017_5715
bx lr bx lr
endfunc check_errata_cve_2017_5715 endfunc check_errata_cve_2017_5715
#if REPORT_ERRATA add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
/*
* Errata printing function for Cortex A17. Must follow AAPCS.
*/
func cortex_a17_errata_report
push {r12, lr}
bl cpu_get_rev_var errata_report_shim cortex_a17
mov r4, r0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A17_852421, cortex_a17, 852421
report_errata ERRATA_A17_852423, cortex_a17, 852423
report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715
pop {r12, lr}
bx lr
endfunc cortex_a17_errata_report
#endif
func cortex_a17_reset_func func cortex_a17_reset_func
mov r5, lr mov r5, lr
@ -139,7 +124,7 @@ func cortex_a17_reset_func
#endif #endif
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
ldr r0, =workaround_bpiall_runtime_exceptions ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR stcopr r0, VBAR
stcopr r0, MVBAR stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */ /* isb will be applied in the course of the reset func */

6
lib/cpus/aarch32/cortex_a9.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -42,7 +42,7 @@ func check_errata_a9_794073
mov r0, #ERRATA_MISSING mov r0, #ERRATA_MISSING
#endif #endif
bx lr bx lr
endfunc check_errata_cve_2017_5715 endfunc check_errata_a9_794073
func check_errata_cve_2017_5715 func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715 #if WORKAROUND_CVE_2017_5715
@ -77,7 +77,7 @@ endfunc cortex_a9_errata_report
func cortex_a9_reset_func func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
ldr r0, =workaround_bpiall_runtime_exceptions ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR stcopr r0, VBAR
stcopr r0, MVBAR stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */ /* isb will be applied in the course of the reset func */