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refactor(arm): replace hard-coded HW_CONFIG DT size

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Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This commit is contained in:
Harrison Mutai 2024-04-11 15:43:21 +00:00
parent 64bd9551b1
commit df960bcc3b
13 changed files with 39 additions and 19 deletions
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5
plat/arm/board/a5ds/fdts/a5ds_fw_config.dts
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@ -1,10 +1,11 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x83000000>;
max-size = <0x01000000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};

5
plat/arm/board/a5ds/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -208,6 +208,9 @@
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/* Define memory configuration for device tree files. */
#define PLAT_ARM_HW_CONFIG_SIZE U(0x01000000)
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of

5
plat/arm/board/fvp/fdts/fvp_fw_config.dts
View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x07f00000>;
max-size = <0x00100000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
secondary-load-address = <0x0 0x82000000>;
};

3
plat/arm/board/fvp/include/platform_def.h
View file

@ -110,6 +110,9 @@
#define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024
/* Define memory configuration for device tree files. */
#define PLAT_ARM_HW_CONFIG_SIZE U(0x10000)
#if SPMC_AT_EL3
/*
* Number of Secure Partitions supported.

6
plat/arm/board/fvp_r/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -90,11 +90,11 @@
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
#define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000)
#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
PLAT_HW_CONFIG_DTB_BASE, \
PLAT_HW_CONFIG_DTB_SIZE, \
PLAT_ARM_HW_CONFIG_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
#define V2M_FVP_R_SYSREGS_BASE UL(0x9c010000)

5
plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts
View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x82000000>;
max-size = <0x01000000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};

5
plat/arm/board/fvp_ve/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -158,6 +158,9 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/* Define memory configuration for device tree files. */
#define PLAT_ARM_HW_CONFIG_SIZE U(0x01000000)
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.

5
plat/arm/board/juno/fdts/juno_fw_config.dts
View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x82000000>;
max-size = <0x8000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};

3
plat/arm/board/juno/include/platform_def.h
View file

@ -36,6 +36,9 @@
* Other platform porting definitions are provided by included headers
*/
/* Define memory configuration for device tree files. */
#define PLAT_ARM_HW_CONFIG_SIZE U(0x8000)
/*
* Required ARM standard platform porting definitions
*/

5
plat/arm/board/morello/fdts/morello_fw_config.dts
View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
/ {
@ -25,7 +26,7 @@
hw-config {
load-address = <0x0 0xFEFF8000>;
max-size = <0x8000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};

3
plat/arm/board/morello/include/platform_def.h
View file

@ -75,6 +75,9 @@
*/
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
/* Define memory configuration for device tree files. */
#define PLAT_ARM_HW_CONFIG_SIZE U(0x8000)
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/

4
plat/arm/board/tc/fdts/tc_fw_config.dts
View file

@ -27,11 +27,11 @@
hw-config {
load-address = <0x0 PLAT_HW_CONFIG_DTB_BASE>;
max-size = <PLAT_HW_CONFIG_DTB_SIZE>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
nt_fw-config {
load-address = <0x0 (PLAT_HW_CONFIG_DTB_BASE + PLAT_HW_CONFIG_DTB_SIZE)>;
load-address = <0x0 (PLAT_HW_CONFIG_DTB_BASE + PLAT_ARM_HW_CONFIG_SIZE)>;
max-size = <0x1000>;
id = <NT_FW_CONFIG_ID>;
};

4
plat/arm/board/tc/include/platform_def.h
View file

@ -88,11 +88,11 @@
MT_MEMORY | MT_RW | MT_SECURE)
#define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
#define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000)
#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \
PLAT_HW_CONFIG_DTB_BASE, \
PLAT_HW_CONFIG_DTB_SIZE, \
PLAT_ARM_HW_CONFIG_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
/*
* Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to