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Add support for Cortex-A57 erratum 826974 workaround

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Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
This commit is contained in:
Sandrine Bailleux 2016-04-14 13:32:31 +01:00
parent 097b787a0e
commit df22d602b6
4 changed files with 44 additions and 0 deletions
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3
docs/cpu-specific-build-macros.md
View file

@ -60,6 +60,9 @@ For Cortex-A57, following errata build flags are defined :
* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 * `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
CPU. This needs to be enabled only for revision r0p0 of the CPU. CPU. This needs to be enabled only for revision r0p0 of the CPU.
* `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
3. CPU Specific optimizations 3. CPU Specific optimizations
------------------------------ ------------------------------

1
include/lib/cpus/aarch64/cortex_a57.h
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@ -61,6 +61,7 @@
******************************************************************************/ ******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_DIS_OVERREAD (1 << 52)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44) #define CPUACTLR_DCC_AS_DCCI (1 << 44)

32
lib/cpus/aarch64/cortex_a57.S
View file

@ -167,6 +167,33 @@ disable_hint:
ret ret
endfunc a57_disable_ldnp_overread endfunc a57_disable_ldnp_overread
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #826974.
* This applies only to revision <= r1p1 of Cortex A57.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Clobbers : x0 - x5
* ---------------------------------------------------
*/
func errata_a57_826974_wa
/*
* Compare x0 against revision r1p1
*/
cmp x0, #0x11
b.ls apply_826974
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
b print_revision_warning
#else
ret
#endif
apply_826974:
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB
msr CPUACTLR_EL1, x1
ret
endfunc errata_a57_826974_wa
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57. * The CPU Ops reset function for Cortex-A57.
* Clobbers: x0-x5, x15, x19, x30 * Clobbers: x0-x5, x15, x19, x30
@ -200,6 +227,11 @@ func cortex_a57_reset_func
bl a57_disable_ldnp_overread bl a57_disable_ldnp_overread
#endif #endif
#if ERRATA_A57_826974
mov x0, x15
bl errata_a57_826974_wa
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Enable the SMP bit. * Enable the SMP bit.
* --------------------------------------------- * ---------------------------------------------

8
lib/cpus/cpu-ops.mk
View file

@ -74,6 +74,10 @@ ERRATA_A57_806969 ?=0
# only to revision r0p0 of the Cortex A57 cpu. # only to revision r0p0 of the Cortex A57 cpu.
ERRATA_A57_813420 ?=0 ERRATA_A57_813420 ?=0
# Flag to apply erratum 826974 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A57 cpu.
ERRATA_A57_826974 ?=0
# Process ERRATA_A53_826319 flag # Process ERRATA_A53_826319 flag
$(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call assert_boolean,ERRATA_A53_826319))
$(eval $(call add_define,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319))
@ -89,3 +93,7 @@ $(eval $(call add_define,ERRATA_A57_806969))
# Process ERRATA_A57_813420 flag # Process ERRATA_A57_813420 flag
$(eval $(call assert_boolean,ERRATA_A57_813420)) $(eval $(call assert_boolean,ERRATA_A57_813420))
$(eval $(call add_define,ERRATA_A57_813420)) $(eval $(call add_define,ERRATA_A57_813420))
# Process ERRATA_A57_826974 flag
$(eval $(call assert_boolean,ERRATA_A57_826974))
$(eval $(call add_define,ERRATA_A57_826974))