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https://github.com/ARM-software/arm-trusted-firmware.git
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stm32mp1: print information about SoC
This information is located in DBGMCU registers. Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30 Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
73680c230f
commit
dec286dd7d
6 changed files with 192 additions and 0 deletions
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@ -56,6 +56,9 @@ uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
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unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
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uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
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/* Print CPU information */
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void stm32mp_print_cpuinfo(void);
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/*
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* Util for clock gating and to get clock rate for stm32 and platform drivers
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* @id: Target clock ID, ID used in clock DT bindings
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@ -272,6 +272,8 @@ void bl2_el3_plat_arch_setup(void)
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panic();
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}
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stm32mp_print_cpuinfo();
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board_model = dt_get_board_model();
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if (board_model != NULL) {
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NOTICE("Model: %s\n", board_model);
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@ -7,6 +7,12 @@
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#ifndef STM32MP1_DBGMCU_H
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#define STM32MP1_DBGMCU_H
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#include <stdint.h>
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/* Get chip version and ID from DBGMCU registers */
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int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version);
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int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id);
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/*
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* Freeze watchdog when a debugger is attached, if the security configuration
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* allows it.
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@ -16,7 +16,13 @@
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#include <stm32mp1_dbgmcu.h>
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#define DBGMCU_IDC U(0x00)
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#define DBGMCU_APB4FZ1 U(0x2C)
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#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
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#define DBGMCU_IDC_REV_ID_SHIFT 16
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
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static uintptr_t get_rcc_base(void)
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@ -47,6 +53,30 @@ static int stm32mp1_dbgmcu_init(void)
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return 0;
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}
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int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version)
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{
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if (stm32mp1_dbgmcu_init() != 0) {
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return -EPERM;
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}
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*chip_version = (mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) &
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DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
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return 0;
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}
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int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id)
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{
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if (stm32mp1_dbgmcu_init() != 0) {
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return -EPERM;
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}
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*chip_dev_id = mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) &
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DBGMCU_IDC_DEV_ID_MASK;
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return 0;
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}
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int stm32mp1_dbgmcu_freeze_iwdg2(void)
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{
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uint32_t dbg_conf;
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@ -22,9 +22,30 @@
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_private.h>
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#endif
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/*******************************************************************************
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* CHIP ID
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******************************************************************************/
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#define STM32MP157C_PART_NB U(0x05000000)
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#define STM32MP157A_PART_NB U(0x05000001)
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#define STM32MP153C_PART_NB U(0x05000024)
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#define STM32MP153A_PART_NB U(0x05000025)
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#define STM32MP151C_PART_NB U(0x0500002E)
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#define STM32MP151A_PART_NB U(0x0500002F)
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#define STM32MP1_REV_B U(0x2000)
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/*******************************************************************************
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* PACKAGE ID
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******************************************************************************/
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#define PKG_AA_LFBGA448 U(4)
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#define PKG_AB_LFBGA354 U(3)
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#define PKG_AC_TFBGA361 U(2)
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#define PKG_AD_TFBGA257 U(1)
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/*******************************************************************************
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* STM32MP1 memory map related constants
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******************************************************************************/
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@ -240,12 +261,22 @@ enum ddr_type {
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/* OTP offsets */
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#define DATA0_OTP U(0)
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#define PART_NUMBER_OTP U(1)
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#define PACKAGE_OTP U(16)
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#define HW2_OTP U(18)
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/* OTP mask */
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/* DATA0 */
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#define DATA0_OTP_SECURED BIT(6)
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/* PART NUMBER */
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#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
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#define PART_NUMBER_OTP_PART_SHIFT 0
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/* PACKAGE */
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#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
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#define PACKAGE_OTP_PKG_SHIFT 27
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/* IWDG OTP */
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#define HW2_OTP_IWDG_HW_POS U(3)
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#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
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@ -68,6 +68,126 @@ unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
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return GPIOA + (bank - GPIO_BANK_A);
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}
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static int get_part_number(uint32_t *part_nb)
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{
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uint32_t part_number;
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uint32_t dev_id;
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if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
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return -1;
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}
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if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
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ERROR("BSEC: PART_NUMBER_OTP Error\n");
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return -1;
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}
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part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
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PART_NUMBER_OTP_PART_SHIFT;
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*part_nb = part_number | (dev_id << 16);
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return 0;
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}
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static int get_cpu_package(uint32_t *cpu_package)
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{
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uint32_t package;
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if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
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ERROR("BSEC: PACKAGE_OTP Error\n");
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return -1;
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}
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*cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
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PACKAGE_OTP_PKG_SHIFT;
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return 0;
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}
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void stm32mp_print_cpuinfo(void)
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{
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const char *cpu_s, *cpu_r, *pkg;
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uint32_t part_number;
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uint32_t cpu_package;
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uint32_t chip_dev_id;
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int ret;
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/* MPUs Part Numbers */
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ret = get_part_number(&part_number);
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if (ret < 0) {
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WARN("Cannot get part number\n");
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return;
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}
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switch (part_number) {
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case STM32MP157C_PART_NB:
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cpu_s = "157C";
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break;
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case STM32MP157A_PART_NB:
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cpu_s = "157A";
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break;
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case STM32MP153C_PART_NB:
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cpu_s = "153C";
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break;
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case STM32MP153A_PART_NB:
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cpu_s = "153A";
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break;
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case STM32MP151C_PART_NB:
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cpu_s = "151C";
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break;
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case STM32MP151A_PART_NB:
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cpu_s = "151A";
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break;
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default:
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cpu_s = "????";
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break;
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}
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/* Package */
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ret = get_cpu_package(&cpu_package);
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if (ret < 0) {
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WARN("Cannot get CPU package\n");
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return;
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}
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switch (cpu_package) {
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case PKG_AA_LFBGA448:
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pkg = "AA";
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break;
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case PKG_AB_LFBGA354:
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pkg = "AB";
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break;
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case PKG_AC_TFBGA361:
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pkg = "AC";
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break;
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case PKG_AD_TFBGA257:
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pkg = "AD";
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break;
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default:
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pkg = "??";
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break;
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}
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/* REVISION */
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ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
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if (ret < 0) {
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WARN("Cannot get CPU version\n");
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return;
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}
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switch (chip_dev_id) {
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case STM32MP1_REV_B:
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cpu_r = "B";
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break;
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default:
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cpu_r = "?";
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break;
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}
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NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
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}
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uint32_t stm32_iwdg_get_instance(uintptr_t base)
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{
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switch (base) {
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