diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index ca9efb6a5..c5058f5cb 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst
@@ -18,9 +18,8 @@ Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
 is the CPUs supported as below:
 
 -  TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
--  TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
--  TC2 has support for Hayes and Cortex A720 Arm CPUs.
-
+-  TC1 has support for Cortex A510, Cortex A715 and Cortex X3.
+-  TC2 has support for Cortex A520, Cortex A720 and Cortex x4.
 
 Boot Sequence
 -------------
diff --git a/include/lib/cpus/aarch64/cortex_hayes.h b/include/lib/cpus/aarch64/cortex_a520.h
similarity index 59%
rename from include/lib/cpus/aarch64/cortex_hayes.h
rename to include/lib/cpus/aarch64/cortex_a520.h
index 82022e9ff..417698152 100644
--- a/include/lib/cpus/aarch64/cortex_hayes.h
+++ b/include/lib/cpus/aarch64/cortex_a520.h
@@ -1,23 +1,23 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_HAYES_H
-#define CORTEX_HAYES_H
+#ifndef CORTEX_A520_H
+#define CORTEX_A520_H
 
-#define CORTEX_HAYES_MIDR					U(0x410FD800)
+#define CORTEX_A520_MIDR					U(0x410FD800)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
-#define CORTEX_HAYES_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A520_CPUECTLR_EL1				S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_HAYES_CPUPWRCTLR_EL1				S3_0_C15_C2_7
-#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define CORTEX_A520_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
-#endif /* CORTEX_HAYES_H */
+#endif /* CORTEX_A520_H */
diff --git a/lib/cpus/aarch64/cortex_hayes.S b/lib/cpus/aarch64/cortex_a520.S
similarity index 51%
rename from lib/cpus/aarch64/cortex_hayes.S
rename to lib/cpus/aarch64/cortex_a520.S
index 445a69187..5bbe86266 100644
--- a/lib/cpus/aarch64/cortex_hayes.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,54 +7,54 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_hayes.h>
+#include <cortex_a520.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Hayes must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Hayes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
-func cortex_hayes_core_pwr_dwn
+func cortex_a520_core_pwr_dwn
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_HAYES_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_HAYES_CPUPWRCTLR_EL1, x0
+	mrs	x0, CORTEX_A520_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A520_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_hayes_core_pwr_dwn
+endfunc cortex_a520_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Cortex Hayes. Must follow AAPCS.
+	 * Errata printing function for Cortex A520. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_hayes_errata_report
+func cortex_a520_errata_report
 	ret
-endfunc cortex_hayes_errata_report
+endfunc cortex_a520_errata_report
 #endif
 
-func cortex_hayes_reset_func
+func cortex_a520_reset_func
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
 	ret
-endfunc cortex_hayes_reset_func
+endfunc cortex_a520_reset_func
 
 	/* ---------------------------------------------
-	 * This function provides Cortex Hayes specific
+	 * This function provides Cortex A520 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -62,16 +62,16 @@ endfunc cortex_hayes_reset_func
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_hayes_regs, "aS"
-cortex_hayes_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_a520_regs, "aS"
+cortex_a520_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_hayes_cpu_reg_dump
-	adr	x6, cortex_hayes_regs
-	mrs	x8, CORTEX_HAYES_CPUECTLR_EL1
+func cortex_a520_cpu_reg_dump
+	adr	x6, cortex_a520_regs
+	mrs	x8, CORTEX_A520_CPUECTLR_EL1
 	ret
-endfunc cortex_hayes_cpu_reg_dump
+endfunc cortex_a520_cpu_reg_dump
 
-declare_cpu_ops cortex_hayes, CORTEX_HAYES_MIDR, \
-	cortex_hayes_reset_func, \
-	cortex_hayes_core_pwr_dwn
+declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \
+	cortex_a520_reset_func, \
+	cortex_a520_core_pwr_dwn
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 3d2f8be20..c9425c5c7 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -59,6 +59,7 @@ ifeq (${HW_ASSISTED_COHERENCY}, 0)
 else
 # AArch64-only cores
 	FPGA_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a510.S			\
+				lib/cpus/aarch64/cortex_a520.S			\
 				lib/cpus/aarch64/cortex_a710.S			\
 				lib/cpus/aarch64/cortex_a715.S			\
 				lib/cpus/aarch64/cortex_a720.S			\
@@ -68,7 +69,6 @@ else
 				lib/cpus/aarch64/neoverse_n1.S			\
 				lib/cpus/aarch64/neoverse_n2.S			\
 				lib/cpus/aarch64/neoverse_v1.S			\
-				lib/cpus/aarch64/cortex_hayes.S			\
 				lib/cpus/aarch64/cortex_chaberton.S		\
 				lib/cpus/aarch64/cortex_blackhawk.S
 
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 4faa98fcf..5a1d83aa0 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -78,7 +78,7 @@ endif
 
 # CPU libraries for TARGET_PLATFORM=2
 ifeq (${TARGET_PLATFORM}, 2)
-TC_CPU_SOURCES	+=	lib/cpus/aarch64/cortex_hayes.S \
+TC_CPU_SOURCES	+=	lib/cpus/aarch64/cortex_a520.S \
 			lib/cpus/aarch64/cortex_a720.S \
 			lib/cpus/aarch64/cortex_x4.S
 endif