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feat(stm32mp1): add helper to enable high speed mode in low voltage

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This new function is used to fill the register(s) responsible to enable
high speed mode for pad in low voltage (<2.7V).

Change-Id: Ib8abc6628bdf51bbe6a866bc6a9bcdeb4a84a8f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2021-01-12 14:45:02 +01:00
parent 1f4513cb79
commit dea02f4eae
1 changed files with 31 additions and 20 deletions
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51
plat/st/stm32mp1/stm32mp1_syscfg.c
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@ -104,24 +104,21 @@ static void disable_io_comp_cell(uintptr_t cmpcr_off)
mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
} }
void stm32mp1_syscfg_init(void) static void enable_high_speed_mode_low_voltage(void)
{
mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
SYSCFG_IOCTRLSETR_HSLVEN_SPI);
}
static void stm32mp1_syscfg_set_hslv(void)
{ {
uint32_t bootr;
uint32_t otp = 0; uint32_t otp = 0;
uint32_t vdd_voltage; uint32_t vdd_voltage;
/*
* Interconnect update : select master using the port 1.
* LTDC = AXI_M9.
*/
mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
/* Disable Pull-Down for boot pin connected to VDD */
bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
SYSCFG_BOOTR_BOOT_MASK;
mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
/* /*
* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI * High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
@ -150,12 +147,7 @@ void stm32mp1_syscfg_init(void)
if (vdd_voltage == 0U) { if (vdd_voltage == 0U) {
WARN("VDD unknown"); WARN("VDD unknown");
} else if (vdd_voltage < 2700000U) { } else if (vdd_voltage < 2700000U) {
mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, enable_high_speed_mode_low_voltage();
SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
SYSCFG_IOCTRLSETR_HSLVEN_SPI);
if (otp == 0U) { if (otp == 0U) {
INFO("Product_below_2v5=0: HSLVEN protected by HW\n"); INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
@ -168,6 +160,25 @@ void stm32mp1_syscfg_init(void)
panic(); panic();
} }
} }
}
void stm32mp1_syscfg_init(void)
{
uint32_t bootr;
/*
* Interconnect update : select master using the port 1.
* LTDC = AXI_M9.
*/
mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
/* Disable Pull-Down for boot pin connected to VDD */
bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
SYSCFG_BOOTR_BOOT_MASK;
mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
stm32mp1_syscfg_set_hslv();
stm32mp1_syscfg_enable_io_compensation_start(); stm32mp1_syscfg_enable_io_compensation_start();
} }