From de310e1e5f0b76b9de2b93759344540e0109c8eb Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 7 Jul 2022 19:30:22 +0800 Subject: [PATCH] feat(mt8188): initialize platform for MediaTek MT8188 - Add basic platform setup. - Add MT8188 documentation at docs/plat/. - Add generic CPU helper functions. - Add basic register address. - Add mtk_pm.c in lib/pm TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen Change-Id: I5f8617c42ffba2c9d3a16f3980cb75fda5624031 --- docs/plat/index.rst | 1 + docs/plat/mt8188.rst | 21 +++++ plat/mediatek/include/mt8188/platform_def.h | 99 +++++++++++++++++++++ plat/mediatek/lib/pm/mtk_pm.c | 18 ++++ plat/mediatek/lib/pm/rules.mk | 14 +++ plat/mediatek/mt8188/aarch64/plat_helpers.S | 45 ++++++++++ plat/mediatek/mt8188/include/plat_helpers.h | 12 +++ plat/mediatek/mt8188/include/plat_macros.S | 38 ++++++++ plat/mediatek/mt8188/include/plat_private.h | 18 ++++ plat/mediatek/mt8188/plat_config.mk | 32 +++++++ plat/mediatek/mt8188/plat_mmap.c | 18 ++++ plat/mediatek/mt8188/plat_topology.c | 70 +++++++++++++++ plat/mediatek/mt8188/platform.mk | 47 ++++++++++ 13 files changed, 433 insertions(+) create mode 100644 docs/plat/mt8188.rst create mode 100644 plat/mediatek/include/mt8188/platform_def.h create mode 100644 plat/mediatek/lib/pm/mtk_pm.c create mode 100644 plat/mediatek/lib/pm/rules.mk create mode 100644 plat/mediatek/mt8188/aarch64/plat_helpers.S create mode 100644 plat/mediatek/mt8188/include/plat_helpers.h create mode 100644 plat/mediatek/mt8188/include/plat_macros.S create mode 100644 plat/mediatek/mt8188/include/plat_private.h create mode 100644 plat/mediatek/mt8188/plat_config.mk create mode 100644 plat/mediatek/mt8188/plat_mmap.c create mode 100644 plat/mediatek/mt8188/plat_topology.c create mode 100644 plat/mediatek/mt8188/platform.mk diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 0cef16a34..1f497e0ef 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -21,6 +21,7 @@ Platform Ports marvell/index mt8183 mt8186 + mt8188 mt8192 mt8195 nvidia-tegra diff --git a/docs/plat/mt8188.rst b/docs/plat/mt8188.rst new file mode 100644 index 000000000..93abaa5cd --- /dev/null +++ b/docs/plat/mt8188.rst @@ -0,0 +1,21 @@ +MediaTek 8188 +============= + +MediaTek 8188 (MT8188) is a 64-bit ARM SoC introduced by MediaTek in 2022. +The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A78. +Cortex-A78 can operate at up to 2.6 GHz. +Cortex-A55 can operate at up to 2.0 GHz. + +Boot Sequence +------------- + +:: + + Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel + + How to Build + ------------ + + .. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- LD=aarch64-linux-gnu-gcc PLAT=mt8188 DEBUG=1 COREBOOT=1 diff --git a/plat/mediatek/include/mt8188/platform_def.h b/plat/mediatek/include/mt8188/platform_def.h new file mode 100644 index 000000000..946ac0413 --- /dev/null +++ b/plat/mediatek/include/mt8188/platform_def.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#define PLAT_PRIMARY_CPU (0x0) + +#define MT_GIC_BASE (0x0C000000) +#define MCUCFG_BASE (0x0C530000) +#define IO_PHYS (0x10000000) + +/* Aggregate of all devices for MMU mapping */ +#define MTK_DEV_RNG0_BASE (MT_GIC_BASE) +#define MTK_DEV_RNG0_SIZE (0x600000) +#define MTK_DEV_RNG1_BASE (IO_PHYS) +#define MTK_DEV_RNG1_SIZE (0x10000000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (IO_PHYS + 0x01002000) +#define UART_BAUDRATE (115200) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_HZ (13000000) +#define SYS_COUNTER_FREQ_IN_MHZ (13) + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE (0x800) + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLAT_MAX_PWR_LVL U(3) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(9) + +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_MCUSYS_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(8) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) + +#define SOC_CHIP_ID U(0x8188) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZRAM_BASE (0x54600000) +#define TZRAM_SIZE (0x00030000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES (16) +#define MAX_MMAP_REGIONS (16) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT (6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/lib/pm/mtk_pm.c b/plat/mediatek/lib/pm/mtk_pm.c new file mode 100644 index 000000000..632a1e702 --- /dev/null +++ b/plat/mediatek/lib/pm/mtk_pm.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +static const plat_psci_ops_t plat_psci_ops = { +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &plat_psci_ops; + + return 0; +} diff --git a/plat/mediatek/lib/pm/rules.mk b/plat/mediatek/lib/pm/rules.mk new file mode 100644 index 000000000..77d040832 --- /dev/null +++ b/plat/mediatek/lib/pm/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := pm + +LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_pm.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/mt8188/aarch64/plat_helpers.S b/plat/mediatek/mt8188/aarch64/plat_helpers.S new file mode 100644 index 000000000..7073ab1a5 --- /dev/null +++ b/plat/mediatek/mt8188/aarch64/plat_helpers.S @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_mediatek_calc_core_pos + +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLAT_PRIMARY_CPU + cset x0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_mediatek_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_mediatek_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); + * + * With this function: CorePos = CoreID (AFF1) + * we do it with x0 = (x0 >> 8) & 0xff + * ----------------------------------------------------- + */ +func plat_mediatek_calc_core_pos + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_mediatek_calc_core_pos diff --git a/plat/mediatek/mt8188/include/plat_helpers.h b/plat/mediatek/mt8188/include/plat_helpers.h new file mode 100644 index 000000000..eb78623ce --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_helpers.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_HELPERS_H +#define PLAT_HELPERS_H + +unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); + +#endif /* PLAT_HELPERS_H */ diff --git a/plat/mediatek/mt8188/include/plat_macros.S b/plat/mediatek/mt8188/include/plat_macros.S new file mode 100644 index 000000000..a6e05a961 --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_macros.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception + * is taken in BL31. + * Clobbers: x0 - x10, x26, x27, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* TODO: leave implementation to GIC owner */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/mediatek/mt8188/include/plat_private.h b/plat/mediatek/mt8188/include/plat_private.h new file mode 100644 index 000000000..4d4ac852f --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk new file mode 100644 index 000000000..e5b3fc57d --- /dev/null +++ b/plat/mediatek/mt8188/plat_config.mk @@ -0,0 +1,32 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Separate text code and read only data +SEPARATE_CODE_AND_RODATA := 1 +# ARMv8.2 and above need enable HW assist coherence +HW_ASSISTED_COHERENCY := 1 +# No need coherency memory because of HW assistency +USE_COHERENT_MEM := 0 +# GIC600 +GICV3_SUPPORT_GIC600 := 1 +# +# MTK options +# +PLAT_EXTRA_RODATA_INCLUDES := 1 + +# Configs for A78 and A55 +CTX_INCLUDE_AARCH32_REGS := 0 +ERRATA_A55_1530923 := 1 +ERRATA_A55_1221012 := 1 +ERRATA_A78_1688305 := 1 +ERRATA_A78_1941498 := 1 +ERRATA_A78_1951500 := 1 +ERRATA_A78_1821534 := 1 +ERRATA_A78_2132060 := 1 +ERRATA_A78_2242635 := 1 + +MACH_MT8188 := 1 +$(eval $(call add_define,MACH_MT8188)) diff --git a/plat/mediatek/mt8188/plat_mmap.c b/plat/mediatek/mt8188/plat_mmap.c new file mode 100644 index 000000000..0d4cbe80c --- /dev/null +++ b/plat/mediatek/mt8188/plat_mmap.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static const mmap_region_t plat_mmap[] = { + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; +DECLARE_MTK_MMAP_REGIONS(plat_mmap); diff --git a/plat/mediatek/mt8188/plat_topology.c b/plat/mediatek/mt8188/plat_topology.c new file mode 100644 index 000000000..9fa285589 --- /dev/null +++ b/plat/mediatek/mt8188/plat_topology.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include + +const unsigned char mtk_power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* Number of children for the root node */ + PLATFORM_MCUSYS_COUNT, + /* Number of children for the mcusys node */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return mtk_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + if ((read_mpidr() & MPIDR_MT_MASK) != 0) { + /* ARMv8.2 arch */ + if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { + return -1; + } + return plat_mediatek_calc_core_pos(mpidr); + } + + mpidr &= MPIDR_AFFINITY_MASK; + + if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { + return -1; + } + + return (cpu_id + (cluster_id * 8)); +} diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk new file mode 100644 index 000000000..bffce41a8 --- /dev/null +++ b/plat/mediatek/mt8188/platform.mk @@ -0,0 +1,47 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} +MTK_SOC := ${PLAT} + +include plat/mediatek/build_helpers/mtk_build_helpers.mk +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -I${MTK_PLAT}/common \ + -I${MTK_PLAT}/include \ + -I${MTK_PLAT}/include/${MTK_SOC} \ + -I${MTK_PLAT} \ + -I${MTK_PLAT_SOC}/include \ + -Idrivers/arm/gic \ + +MODULES-y += $(MTK_PLAT)/common +MODULES-y += $(MTK_PLAT)/lib/mtk_init +MODULES-y += $(MTK_PLAT)/lib/pm + +PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \ + drivers/ti/uart/aarch64/16550_console.S \ + lib/bl_aux_params/bl_aux_params.c + +BL31_SOURCES += drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a78.S \ + ${GICV3_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/common/aarch64/crash_console_helpers.S \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/params_setup.c \ + ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ + $(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c \ + $(MTK_PLAT)/$(MTK_SOC)/plat_topology.c + +include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk + +include lib/coreboot/coreboot.mk