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Merge "fix(errata): workaround for Cortex-A710 erratum 2058056" into integration
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commit
de278f333b
4 changed files with 55 additions and 1 deletions
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@ -401,6 +401,10 @@ For Cortex-A710, the following errata build flags are defined :
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Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
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Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
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is still open.
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is still open.
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- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
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Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
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of the CPU and is still open.
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For Neoverse N2, the following errata build flags are defined :
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For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
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- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
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@ -25,7 +25,7 @@
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* CPU Auxiliary Control register specific definitions.
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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/*******************************************************************************
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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* CPU Auxiliary Control register specific definitions.
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@ -33,4 +33,12 @@
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#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#endif /* CORTEX_A710_H */
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#endif /* CORTEX_A710_H */
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@ -188,6 +188,34 @@ func check_errata_2083908
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b cpu_rev_var_range
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b cpu_rev_var_range
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endfunc check_errata_2083908
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endfunc check_errata_2083908
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/* ---------------------------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 2058056.
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* This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still
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* open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------------
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*/
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func errata_a710_2058056_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_2058056
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cbz x0, 1f
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mrs x1, CORTEX_A710_CPUECTLR2_EL1
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mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
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msr CORTEX_A710_CPUECTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_a710_2058056_wa
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func check_errata_2058056
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2058056
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/* ----------------------------------------------------
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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* ----------------------------------------------------
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@ -223,6 +251,7 @@ func cortex_a710_errata_report
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report_errata ERRATA_A710_2055002, cortex_a710, 2055002
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report_errata ERRATA_A710_2055002, cortex_a710, 2055002
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report_errata ERRATA_A710_2017096, cortex_a710, 2017096
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report_errata ERRATA_A710_2017096, cortex_a710, 2017096
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report_errata ERRATA_A710_2083908, cortex_a710, 2083908
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report_errata ERRATA_A710_2083908, cortex_a710, 2083908
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report_errata ERRATA_A710_2058056, cortex_a710, 2058056
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ldp x8, x30, [sp], #16
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ldp x8, x30, [sp], #16
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ret
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ret
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@ -262,6 +291,11 @@ func cortex_a710_reset_func
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mov x0, x18
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mov x0, x18
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bl errata_a710_2083908_wa
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bl errata_a710_2083908_wa
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#endif
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#endif
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#if ERRATA_A710_2058056
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mov x0, x18
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bl errata_a710_2058056_wa
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#endif
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isb
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isb
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ret x19
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ret x19
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endfunc cortex_a710_reset_func
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endfunc cortex_a710_reset_func
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@ -437,6 +437,10 @@ ERRATA_A710_2081180 ?=0
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# to revision r2p0 of the Cortex-A710 cpu and is still open.
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# to revision r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2083908 ?=0
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ERRATA_A710_2083908 ?=0
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# Flag to apply erratum 2058056 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2058056 ?=0
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# Flag to apply erratum 2067956 workaround during reset. This erratum applies
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# Flag to apply erratum 2067956 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2067956 ?=0
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ERRATA_N2_2067956 ?=0
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@ -834,6 +838,10 @@ $(eval $(call add_define,ERRATA_A710_2081180))
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$(eval $(call assert_boolean,ERRATA_A710_2083908))
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$(eval $(call assert_boolean,ERRATA_A710_2083908))
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$(eval $(call add_define,ERRATA_A710_2083908))
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$(eval $(call add_define,ERRATA_A710_2083908))
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# Process ERRATA_A710_2058056 flag
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$(eval $(call assert_boolean,ERRATA_A710_2058056))
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$(eval $(call add_define,ERRATA_A710_2058056))
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# Process ERRATA_N2_2067956 flag
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# Process ERRATA_N2_2067956 flag
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$(eval $(call assert_boolean,ERRATA_N2_2067956))
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$(eval $(call assert_boolean,ERRATA_N2_2067956))
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$(eval $(call add_define,ERRATA_N2_2067956))
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$(eval $(call add_define,ERRATA_N2_2067956))
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