diff --git a/drivers/cadence/combo_phy/cdns_combo_phy.c b/drivers/cadence/combo_phy/cdns_combo_phy.c new file mode 100644 index 000000000..f00d0c100 --- /dev/null +++ b/drivers/cadence/combo_phy/cdns_combo_phy.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value) +{ + uint32_t data = 0U; + uint32_t value = 0U; + + /* Get PHY register address, write HRS04*/ + value = mmio_read_32(phy_reg_addr); + value &= ~PHY_REG_ADDR_MASK; + value |= phy_reg_addr_value; + mmio_write_32(phy_reg_addr, value); + data = mmio_read_32(phy_reg_addr); + if ((data & PHY_REG_ADDR_MASK) != phy_reg_addr_value) { + ERROR("PHY_REG_ADDR is not set properly\n"); + return -ENXIO; + } + + /* Get PHY register data, write HRS05 */ + value &= ~PHY_REG_DATA_MASK; + value |= phy_reg_data_value; + mmio_write_32(phy_reg_data, value); + data = mmio_read_32(phy_reg_data); + if (data != phy_reg_data_value) { + ERROR("PHY_REG_DATA is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_sd_card_detect(void) +{ + uint32_t value = 0; + + /* Card detection */ + do { + value = mmio_read_32(SDMMC_CDN(SRS09)); + /* Wait for card insertion. SRS09.CI = 1 */ + } while ((value & (1 << SDMMC_CDN_CI)) == 0); + + if ((value & (1 << SDMMC_CDN_CI)) == 0) { + ERROR("Card does not detect\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_emmc_card_reset(void) +{ + uint32_t _status = 0; + + /* Reset embedded card */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + mdelay(68680); /* ~68680us */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(340); /* ~340us */ + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + + return 0; +} diff --git a/drivers/cadence/emmc/cdns_sdmmc.c b/drivers/cadence/emmc/cdns_sdmmc.c new file mode 100644 index 000000000..d2cd4d6a5 --- /dev/null +++ b/drivers/cadence/emmc/cdns_sdmmc.c @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Card busy and present */ +#define CARD_BUSY 1 +#define CARD_NOT_BUSY 0 + +/* 500 ms delay to read the RINST register */ +#define DELAY_MS_SRS_READ 500 +#define DELAY_RES 10 + +/* SRS12 error mask */ +#define SRS12_ERR_MASK 0xFFFF8000 + +/* Check DV dfi_init val=0 */ +#define IO_MASK_END_DATA 0x0 + +/* Check DV dfi_init val=2; DDR Mode */ +#define IO_MASK_END_DATA_DDR 0x2 +#define IO_MASK_START_DATA 0x0 +#define DATA_SELECT_OE_END_DATA 0x1 + +#define TIMEOUT 100000 + +/* General define */ +#define SDHC_REG_MASK UINT_MAX +#define SD_HOST_BLOCK_SIZE 0x200 +#define DTCVVAL_DEFAULT_VAL 0xE +#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024 +#define CDNSMMC_ADDRESS_MASK U(0x0f) +#define CONFIG_CDNS_DESC_COUNT 8 + +void cdns_init(void); +int cdns_send_cmd(struct mmc_cmd *cmd); +int cdns_set_ios(unsigned int clk, unsigned int width); +int cdns_prepare(int lba, uintptr_t buf, size_t size); +int cdns_read(int lba, uintptr_t buf, size_t size); +int cdns_write(int lba, uintptr_t buf, size_t size); + +const struct mmc_ops cdns_sdmmc_ops = { + .init = cdns_init, + .send_cmd = cdns_send_cmd, + .set_ios = cdns_set_ios, + .prepare = cdns_prepare, + .read = cdns_read, + .write = cdns_write, +}; + +struct cdns_sdmmc_params cdns_params; +struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg; +struct cdns_sdmmc_sdhc sdmmc_sdhc_reg; +#ifdef CONFIG_DMA_ADDR_T_64BIT +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT]; +#else +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(32); +#endif + +bool data_cmd; + +int cdns_wait_ics(uint16_t timeout, uint32_t cdn_srs_res) +{ + /* Clock for sdmclk and sdclk */ + uint32_t count = 0; + uint32_t data = 0; + + /* Wait status command response ready */ + do { + data = mmio_read_32(cdn_srs_res); + count++; + if (count >= timeout) { + return -ETIMEDOUT; + } + } while ((data & (1 << SDMMC_CDN_ICS)) == 0); + + return 0; +} + +int cdns_busy(void) +{ + unsigned int data; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS09); + return (data & STATUS_DATA_BUSY) ? CARD_BUSY : CARD_NOT_BUSY; +} + +int cdns_vol_reset(void) +{ + /* Reset embedded card */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(500); + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + return 0; +} + +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + /* Values are taken by the reference of cadence IP documents */ + combo_phy_reg->cp_clk_wr_delay = 0; + combo_phy_reg->cp_clk_wrdqs_delay = 0; + combo_phy_reg->cp_data_select_oe_end = 0; + combo_phy_reg->cp_dll_bypass_mode = 1; + combo_phy_reg->cp_dll_locked_mode = 0; + combo_phy_reg->cp_dll_start_point = 0; + combo_phy_reg->cp_gate_cfg_always_on = 1; + combo_phy_reg->cp_io_mask_always_on = 0; + combo_phy_reg->cp_io_mask_end = 0; + combo_phy_reg->cp_io_mask_start = 0; + combo_phy_reg->cp_rd_del_sel = 52; + combo_phy_reg->cp_read_dqs_cmd_delay = 0; + combo_phy_reg->cp_read_dqs_delay = 0; + combo_phy_reg->cp_sw_half_cycle_shift = 0; + combo_phy_reg->cp_sync_method = 1; + combo_phy_reg->cp_underrun_suppress = 1; + combo_phy_reg->cp_use_ext_lpbk_dqs = 1; + combo_phy_reg->cp_use_lpbk_dqs = 1; + combo_phy_reg->cp_use_phony_dqs = 1; + combo_phy_reg->cp_use_phony_dqs_cmd = 1; + + sdhc_reg->sdhc_extended_rd_mode = 1; + sdhc_reg->sdhc_extended_wr_mode = 1; + sdhc_reg->sdhc_hcsdclkadj = 0; + sdhc_reg->sdhc_idelay_val = 0; + sdhc_reg->sdhc_rdcmd_en = 1; + sdhc_reg->sdhc_rddata_en = 1; + sdhc_reg->sdhc_rw_compensate = 9; + sdhc_reg->sdhc_sdcfsh = 0; + sdhc_reg->sdhc_sdcfsl = 1; + sdhc_reg->sdhc_wrcmd0_dly = 1; + sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0; + sdhc_reg->sdhc_wrcmd1_dly = 0; + sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata0_dly = 1; + sdhc_reg->sdhc_wrdata0_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata1_dly = 0; + sdhc_reg->sdhc_wrdata1_sdclk_dly = 0; +} + +static int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program PHY_DQS_TIMING_REG */ + value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) | + (CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) | + (CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) | + (CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQS_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_GATE_LPBK_CTRL_REG */ + value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) | + (CP_SW_HALF_CYCLE_SHIFT(combo_phy_reg->cp_sw_half_cycle_shift)) | + (CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) | + (CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) | + (CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_MASTER_CTRL_REG */ + value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) + | (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_SLAVE_CTRL_REG */ + value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) + | (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) + | (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) + | (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_CTRL_REG */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS04, COMBO_PHY_REG + + PHY_CTRL_REG); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS05); + + /* phony_dqs_timing=0 */ + value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS05, value); + + /* switch off DLL_RESET */ + do { + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value |= SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + /* polling PHY_INIT_COMPLETE */ + } while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE); + + /* program PHY_DQ_TIMING_REG */ + combo_phy_reg->cp_io_mask_end = 0U; + value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) + | (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) + | (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) + | (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end)); + + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQ_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + return 0; +} + +int cdns_read(int lba, uintptr_t buf, size_t size) +{ + inv_dcache_range(buf, size); + + return 0; +} + +void cdns_init(void) +{ + /* Dummy function pointer for cdns_init. */ +} + +int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size) +{ + data_cmd = true; + struct cdns_idmac_desc *desc; + uint32_t desc_cnt, i; + uint64_t desc_base; + + assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) && + (cdns_params.desc_size > 0) && + ((MMC_REG_BASE & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_base & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_size & MMC_BLOCK_MASK) == 0)); + + flush_dcache_range(dma_buff, size); + + desc_cnt = (size + (CDMMC_DMA_MAX_BUFFER_SIZE) - 1) / (CDMMC_DMA_MAX_BUFFER_SIZE); + assert(desc_cnt * sizeof(struct cdns_idmac_desc) < cdns_params.desc_size); + + if (desc_cnt > CONFIG_CDNS_DESC_COUNT) { + ERROR("Requested data transfer length %ld is greater than configured length %d", + size, (CONFIG_CDNS_DESC_COUNT * CDMMC_DMA_MAX_BUFFER_SIZE)); + return -EINVAL; + } + + desc = (struct cdns_idmac_desc *)cdns_params.desc_base; + desc_base = (uint64_t)desc; + i = 0; + + while ((i + 1) < desc_cnt) { + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + desc->reserved = 0; + desc->len = MAX_64KB_PAGE; + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_hi = (dma_buff >> 32) & 0xffffffff; +#endif + size -= CDMMC_DMA_MAX_BUFFER_SIZE; + desc++; + i++; + } + + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA | + ADMA_DESC_ATTR_END; + desc->reserved = 0; + desc->len = size; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); + desc->addr_hi = (dma_buff >> 32) & UINT_MAX; +#else + desc->addr_lo = (dma_buff & UINT_MAX); +#endif + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS22, (uint32_t)desc_base); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS23, (uint32_t)(desc_base >> 32)); + flush_dcache_range(cdns_params.desc_base, + desc_cnt * CDMMC_DMA_MAX_BUFFER_SIZE); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS01, + ((512 << BLOCK_SIZE) | ((size/512) << BLK_COUNT_CT) | SDMA_BUF)); + return 0; +} + +static void cdns_host_set_clk(int clk) +{ + uint32_t ret = 0; + uint32_t sdclkfsval = 0; + uint32_t dtcvval = DTCVVAL_DEFAULT_VAL; + + sdclkfsval = (cdns_params.clk_rate / 2000) / clk; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + } + + /* Enable DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & + ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) + & SDHC_EXTENDED_WR_MODE_MASK) | (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); +} + +int cdns_set_ios(unsigned int clk, unsigned int width) +{ + + switch (width) { + case MMC_BUS_WIDTH_1: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), LEDC_OFF); + break; + case MMC_BUS_WIDTH_4: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), DTW_4BIT); + break; + case MMC_BUS_WIDTH_8: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), EDTW_8BIT); + break; + default: + assert(0); + break; + } + cdns_host_set_clk(clk); + + return 0; +} + +int cdns_sdmmc_write_sd_host_reg(uint32_t addr, uint32_t data) +{ + uint32_t value = 0; + + value = mmio_read_32(addr); + value &= ~SDHC_REG_MASK; + value |= data; + mmio_write_32(addr, value); + value = mmio_read_32(addr); + if (value != data) { + ERROR("SD host address is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_write(int lba, uintptr_t buf, size_t size) +{ + return 0; +} + +static int cdns_init_hrs_io(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program HRS09, register 42 */ + value = (SDHC_RDDATA_EN(sdhc_reg->sdhc_rddata_en)) + | (SDHC_RDCMD_EN(sdhc_reg->sdhc_rdcmd_en)) + | (SDHC_EXTENDED_WR_MODE(sdhc_reg->sdhc_extended_wr_mode)) + | (SDHC_EXTENDED_RD_MODE(sdhc_reg->sdhc_extended_rd_mode)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + if (ret != 0) { + ERROR("Program HRS09 failed"); + return ret; + } + + /* program HRS10, register 43 */ + value = (SDHC_HCSDCLKADJ(sdhc_reg->sdhc_hcsdclkadj)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS10, value); + if (ret != 0) { + ERROR("Program HRS10 failed"); + return ret; + } + + /* program HRS16, register 48 */ + value = (SDHC_WRDATA1_SDCLK_DLY(sdhc_reg->sdhc_wrdata1_sdclk_dly)) + | (SDHC_WRDATA0_SDCLK_DLY(sdhc_reg->sdhc_wrdata0_sdclk_dly)) + | (SDHC_WRCMD1_SDCLK_DLY(sdhc_reg->sdhc_wrcmd1_sdclk_dly)) + | (SDHC_WRCMD0_SDCLK_DLY(sdhc_reg->sdhc_wrcmd0_sdclk_dly)) + | (SDHC_WRDATA1_DLY(sdhc_reg->sdhc_wrdata1_dly)) + | (SDHC_WRDATA0_DLY(sdhc_reg->sdhc_wrdata0_dly)) + | (SDHC_WRCMD1_DLY(sdhc_reg->sdhc_wrcmd1_dly)) + | (SDHC_WRCMD0_DLY(sdhc_reg->sdhc_wrcmd0_dly)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS16, value); + if (ret != 0) { + ERROR("Program HRS16 failed"); + return ret; + } + + /* program HRS07, register 40 */ + value = (SDHC_RW_COMPENSATE(sdhc_reg->sdhc_rw_compensate)) + | (SDHC_IDELAY_VAL(sdhc_reg->sdhc_idelay_val)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS07, value); + if (ret != 0) { + ERROR("Program HRS07 failed"); + return ret; + } + + return ret; +} + +static int cdns_hc_set_clk(struct cdns_sdmmc_params *cdn_sdmmc_dev_mode_params) +{ + uint32_t ret = 0; + uint32_t dtcvval, sdclkfsval; + + dtcvval = DTC_VAL; + sdclkfsval = 0; + + if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_DS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR12) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR_BC)) { + sdclkfsval = 4; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_HS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR25) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_DDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR)) { + sdclkfsval = 2; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_DDR) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400es)) { + sdclkfsval = 1; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR104) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS200)) { + sdclkfsval = 0; + } + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + return ret; + } + + /* Enable DLL reset */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) & ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), + (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & SDHC_EXTENDED_WR_MODE_MASK) | + (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); + return 0; +} + +int cdns_reset(void) +{ + uint32_t data = 0; + uint32_t count = 0; + uint32_t value = 0; + + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + value &= ~(0xFFFF); + value |= 0x0; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, value); + udelay(500); + + /* Software reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS00, 1); + /* Wait status command response ready */ + do { + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS00); + count++; + if (count >= 5000) { + return -ETIMEDOUT; + } + /* Wait for HRS00.SWR */ + } while ((data & 1) == 1); + + /* Step 1, switch on DLL_RESET */ + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value &= ~SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + + return 0; +} + +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg) +{ + int ret = 0; + + ret = cdns_reset(); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_init_hrs_io(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program init for HRS reg is failed"); + return ret; + } + + ret = cdns_sd_card_detect(); + if (ret != 0) { + ERROR("SD card does not detect"); + return ret; + } + + ret = cdns_vol_reset(); + if (ret != 0) { + ERROR("eMMC card reset failed"); + return ret; + } + + ret = cdns_hc_set_clk(&cdns_params); + if (ret != 0) { + ERROR("hc set clk failed"); + return ret; + } + + return 0; +} + +void cdns_srs10_value_toggle(uint8_t write_val, uint8_t prev_val) +{ + uint32_t data_op = 0U; + + data_op = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, (data_op & (prev_val << 0))); + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, data_op | (write_val << 0)); +} + +void cdns_srs11_srs15_config(uint32_t srs11_val, uint32_t srs15_val) +{ + uint32_t data = 0U; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (data | srs11_val)); + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS15); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS15, (data | srs15_val)); +} + +int cdns_send_cmd(struct mmc_cmd *cmd) +{ + uint32_t op = 0, ret = 0; + uint8_t write_value = 0, prev_val = 0; + uint32_t value; + int32_t timeout; + uint32_t cmd_indx; + uint32_t status = 0, srs15_val = 0, srs11_val = 0; + uint32_t status_check = 0; + + assert(cmd); + cmd_indx = (cmd->cmd_idx) << COM_IDX; + + if (data_cmd) { + switch (cmd->cmd_idx) { + case SD_SWITCH: + op = DATA_PRESENT; + write_value = ADMA2_32 | DT_WIDTH; + prev_val = ADMA2_32 | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + srs15_val = BIT_AD_64 | HV4E | V18SE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_WRITE_SINGLE_BLOCK: + case SD_READ_SINGLE_BLOCK: + op = DATA_PRESENT; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_WRITE_MULTIPLE_BLOCK: + case SD_READ_MULTIPLE_BLOCK: + op = DATA_PRESENT | AUTO_CMD_EN | MULTI_BLK_READ; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_APP_SEND_SCR: + op = DATA_PRESENT; + write_value = ADMA2_32 | LEDC; + prev_val = LEDC; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = BIT_AD_64 | HV4E | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = DATA_PRESENT | CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } else { + switch (cmd->cmd_idx) { + case SD_GO_IDLE_STATE: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_ALL_SEND_CID: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E | V18SE; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_STOP_TRANSMISSION: + op = CMD_STOP_ABORT_CMD; + break; + + case SD_SEND_STATUS: + break; + + case 1: + cmd->cmd_arg = 0; + break; + + case SD_SELECT_CARD: + op = MULTI_BLK_READ; + break; + + case SD_APP_CMD: + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } + + switch (cmd->resp_type) { + case MMC_RESPONSE_NONE: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN; + break; + + case MMC_RESPONSE_R2: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_136 | CMD_CHECK_RESP_CRC; + break; + + case MMC_RESPONSE_R3: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_48; + break; + + case MMC_RESPONSE_R1: + if ((cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK) || (cmd->cmd_idx + == SD_WRITE_MULTIPLE_BLOCK)) { + op |= DMA_ENABLED | BLK_CNT_EN | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } else { + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } + break; + + default: + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | MULTI_BLK_READ | + RES_TYPE_SEL_48 | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + break; + } + + timeout = TIMEOUT; + do { + udelay(100); + ret = cdns_busy(); + if (--timeout <= 0) { + udelay(50); + panic(); + } + } while (ret); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS12, UINT_MAX); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS02, cmd->cmd_arg); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS14, 0x00000000); + if (cmd_indx == 1) + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, SDHC_CDNS_SRS03_VALUE); + else + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, op | cmd_indx); + + timeout = TIMEOUT; + do { + udelay(500); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS12); + } while (((value & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0)); + + timeout = TIMEOUT; + + if (data_cmd) { + data_cmd = false; + do { + udelay(250); + } while (((value & TRAN_COMP) == 0) && (timeout-- > 0)); + } + + status_check = value & SRS12_ERR_MASK; + if (status_check != 0U) { + ERROR("SD host controller send command failed, SRS12 = %x", status); + return -1; + } + + if ((op & RES_TYPE_SEL_48) || (op & RES_TYPE_SEL_136)) { + cmd->resp_data[0] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS04); + if (op & RES_TYPE_SEL_136) { + cmd->resp_data[1] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS05); + cmd->resp_data[2] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS06); + cmd->resp_data[3] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS07); + } + } + + return 0; +} diff --git a/drivers/cadence/nand/cdns_nand.c b/drivers/cadence/nand/cdns_nand.c new file mode 100644 index 000000000..5a6626262 --- /dev/null +++ b/drivers/cadence/nand/cdns_nand.c @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* NAND flash device information struct */ +static cnf_dev_info_t dev_info; + +/* Scratch buffers for read and write operations */ +static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + +/* Wait for controller to be in idle state */ +static inline void cdns_nand_wait_idle(void) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_CTRL_BUSY(reg) != 0U); +} + +/* Wait for given thread to be in ready state */ +static inline void cdns_nand_wait_thread_ready(uint8_t thread_id) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(TRD_STATUS)); + reg &= (1U << (uint32_t)thread_id); + } while (reg != 0U); +} + +/* Check if the last operation/command in selected thread is completed */ +static int cdns_nand_last_opr_status(uint8_t thread_id) +{ + uint8_t nthreads = 0U; + uint32_t reg = 0U; + + /* Get number of threads */ + reg = mmio_read_32(CNF_CTRLPARAM(FEATURE)); + nthreads = CNF_GET_NTHREADS(reg); + + if (thread_id > nthreads) { + ERROR("%s: Invalid thread ID\n", __func__); + return -EINVAL; + } + + /* Select thread */ + mmio_write_32(CNF_CMDREG(CMD_STAT_PTR), (uint32_t)thread_id); + + uint32_t err_mask = CNF_ECMD | CNF_EECC | CNF_EDEV | CNF_EDQS | CNF_EFAIL | + CNF_EBUS | CNF_EDI | CNF_EPAR | CNF_ECTX | CNF_EPRO; + + do { + udelay(CNF_DEF_DELAY_US * 2); + reg = mmio_read_32(CNF_CMDREG(CMD_STAT)); + } while ((reg & CNF_CMPLT) == 0U); + + /* last operation is completed, make sure no other error bits are set */ + if ((reg & err_mask) == 1U) { + ERROR("%s, CMD_STATUS:0x%x\n", __func__, reg); + return -EIO; + } + + return 0; +} + +/* Set feature command */ +int cdns_nand_set_feature(uint8_t feat_addr, uint8_t feat_val, uint8_t thread_id) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(thread_id); + + /* Set feature address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), (uint32_t)feat_addr); + /* Set feature volume */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (uint32_t)feat_val); + + /* Set feature command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_SET_FEATURE << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Reset command to the selected device */ +int cdns_nand_reset(uint8_t thread_id) +{ + /* Operation is executed in selected thread */ + cdns_nand_wait_thread_ready(thread_id); + + /* Select memory */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Issue reset command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_RESET_ASYNC << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Set operation work mode */ +static void cdns_nand_set_opr_mode(uint8_t opr_mode) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Reset DLL PHY */ + uint32_t reg = mmio_read_32(CNF_MINICTRL(DLL_PHY_CTRL)); + + reg &= ~(1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); + + if (opr_mode == CNF_OPR_WORK_MODE_SDR) { + /* Combo PHY Control Timing Block register settings */ + mmio_write_32(CP_CTB(CTRL_REG), CP_CTRL_REG_SDR); + mmio_write_32(CP_CTB(TSEL_REG), CP_TSEL_REG_SDR); + + /* Combo PHY DLL register settings */ + mmio_write_32(CP_DLL(DQ_TIMING_REG), CP_DQ_TIMING_REG_SDR); + mmio_write_32(CP_DLL(DQS_TIMING_REG), CP_DQS_TIMING_REG_SDR); + mmio_write_32(CP_DLL(GATE_LPBK_CTRL_REG), CP_GATE_LPBK_CTRL_REG_SDR); + mmio_write_32(CP_DLL(MASTER_CTRL_REG), CP_DLL_MASTER_CTRL_REG_SDR); + + /* Async mode timing settings */ + mmio_write_32(CNF_MINICTRL(ASYNC_TOGGLE_TIMINGS), + (2 << CNF_ASYNC_TIMINGS_TRH) | + (4 << CNF_ASYNC_TIMINGS_TRP) | + (2 << CNF_ASYNC_TIMINGS_TWH) | + (4 << CNF_ASYNC_TIMINGS_TWP)); + + /* Set extended read and write mode */ + reg |= (1 << CNF_DLL_PHY_EXT_RD_MODE); + reg |= (1 << CNF_DLL_PHY_EXT_WR_MODE); + + /* Set operation work mode in common settings */ + uint32_t data = mmio_read_32(CNF_MINICTRL(CMN_SETTINGS)); + + data |= (CNF_OPR_WORK_MODE_SDR << CNF_CMN_SETTINGS_OPR); + mmio_write_32(CNF_MINICTRL(CMN_SETTINGS), data); + + } else if (opr_mode == CNF_OPR_WORK_MODE_NVDDR) { + ; /* ToDo: add DDR mode settings also once available on SIMICS */ + } else { + ; + } + + reg |= (1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); +} + +/* Data transfer configuration */ +static void cdns_nand_transfer_config(void) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Configure data transfer parameters */ + mmio_write_32(CNF_CTRLCFG(TRANS_CFG0), 1); + + /* ECC is disabled */ + mmio_write_32(CNF_CTRLCFG(ECC_CFG0), 0); + + /* DMA burst select */ + mmio_write_32(CNF_CTRLCFG(DMA_SETTINGS), + (CNF_DMA_BURST_SIZE_MAX << CNF_DMA_SETTINGS_BURST) | + (1 << CNF_DMA_SETTINGS_OTE)); + + /* Enable pre-fetching for 1K */ + mmio_write_32(CNF_CTRLCFG(FIFO_TLEVEL), + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_POS) | + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_DMA_SIZE)); + + /* Select access type */ + mmio_write_32(CNF_CTRLCFG(MULTIPLANE_CFG), 0); + mmio_write_32(CNF_CTRLCFG(CACHE_CFG), 0); +} + +/* Update the nand flash device info */ +static int cdns_nand_update_dev_info(void) +{ + uint32_t reg = 0U; + + /* Read the device type and number of LUNs */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_PARAMS0)); + dev_info.type = CNF_GET_DEV_TYPE(reg); + if (dev_info.type == CNF_DT_UNKNOWN) { + ERROR("%s: device type unknown\n", __func__); + return -ENXIO; + } + dev_info.nluns = CNF_GET_NLUNS(reg); + + /* Pages per block */ + reg = mmio_read_32(CNF_CTRLCFG(DEV_LAYOUT)); + dev_info.npages_per_block = CNF_GET_NPAGES_PER_BLOCK(reg); + + /* Sector size and last sector size */ + reg = mmio_read_32(CNF_CTRLCFG(TRANS_CFG1)); + dev_info.sector_size = CNF_GET_SCTR_SIZE(reg); + dev_info.last_sector_size = CNF_GET_LAST_SCTR_SIZE(reg); + + /* Page size and spare size */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_AREA)); + dev_info.page_size = CNF_GET_PAGE_SIZE(reg); + dev_info.spare_size = CNF_GET_SPARE_SIZE(reg); + + /* Device blocks per LUN */ + dev_info.nblocks_per_lun = mmio_read_32(CNF_CTRLPARAM(DEV_BLOCKS_PLUN)); + + /* Calculate block size and total device size */ + dev_info.block_size = (dev_info.npages_per_block * dev_info.page_size); + dev_info.total_size = (dev_info.block_size * dev_info.nblocks_per_lun * + dev_info.nluns); + + VERBOSE("CNF params: page %d, spare %d, block %d, total %lld\n", + dev_info.page_size, dev_info.spare_size, + dev_info.block_size, dev_info.total_size); + + return 0; +} + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void) +{ + uint32_t reg = 0U; + int ret = 0; + + do { + /* Read controller status register for init complete */ + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_INIT_COMP(reg) == 0); + + ret = cdns_nand_update_dev_info(); + if (ret != 0) { + return ret; + } + + INFO("CNF: device discovery process completed and device type %d\n", + dev_info.type); + + /* Enable data integrity, enable CRC and parity */ + reg = mmio_read_32(CNF_DI(CONTROL)); + reg |= (1 << CNF_DI_PAR_EN); + reg |= (1 << CNF_DI_CRC_EN); + mmio_write_32(CNF_DI(CONTROL), reg); + + /* Status polling mode, device control and status register */ + cdns_nand_wait_idle(); + reg = mmio_read_32(CNF_CTRLCFG(DEV_STAT)); + reg = reg & ~1; + mmio_write_32(CNF_CTRLCFG(DEV_STAT), reg); + + /* Set operation work mode */ + cdns_nand_set_opr_mode(CNF_OPR_WORK_MODE_SDR); + + /* Set data transfer configuration parameters */ + cdns_nand_transfer_config(); + + return 0; +} + +/* erase: Block erase command */ +int cdns_nand_erase(uint32_t offset, uint32_t size) +{ + /* Determine the starting block offset i.e row address */ + uint32_t row_address = dev_info.npages_per_block * offset; + + /* Wait for thread to be in ready state */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /*Set row address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Operation bank number */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Block erase command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_ERASE << CNF_CMDREG0_CMD); + reg |= (((size-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for erase operation to complete */ + return cdns_nand_last_opr_status(CNF_DEF_TRD); +} + +/* io mtd functions */ +int cdns_nand_init_mtd(unsigned long long *size, unsigned int *erase_size) +{ + *size = dev_info.total_size; + *erase_size = dev_info.block_size; + + return 0; +} + +/* NAND Flash page read */ +static int cdns_nand_read_page(uint32_t block, uint32_t page, uintptr_t buffer) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /* Select device */ + mmio_write_32(CNF_CMDREG(CMD_REG4), + (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Set host memory address for DMA transfers */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (buffer & 0xFFFF)); + mmio_write_32(CNF_CMDREG(CMD_REG3), ((buffer >> 32) & 0xFFFF)); + + /* Set row address */ + uint32_t row_address = 0U; + + row_address |= ((page & 0x3F) | (block << 6)); + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Page read command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_DMA_MASTER_SEL << CNF_CMDREG0_DMA); + reg |= (CNF_CT_PAGE_READ << CNF_CMDREG0_CMD); + reg |= (((CNF_READ_SINGLE_PAGE-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for read operation to complete */ + if (cdns_nand_last_opr_status(CNF_DEF_TRD)) { + ERROR("%s: Page read failed\n", __func__); + return -EIO; + } + + return 0; +} + +int cdns_nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *out_length) +{ + uint32_t block = offset / dev_info.block_size; + uint32_t end_block = (offset + length - 1U) / dev_info.block_size; + uint32_t page_start = (offset % dev_info.block_size) / dev_info.page_size; + uint32_t start_offset = offset % dev_info.page_size; + uint32_t nb_pages = dev_info.block_size / dev_info.page_size; + uint32_t bytes_read = 0U; + uint32_t page = 0U; + int result = 0; + + VERBOSE("CNF: block %u-%u, page_start %u, len %zu, offset %u\n", + block, end_block, page_start, length, offset); + + if ((offset >= dev_info.total_size) || + (offset + length-1 >= dev_info.total_size) || + (length == 0U)) { + ERROR("CNF: Invalid read parameters\n"); + return -EINVAL; + } + + *out_length = 0UL; + + while (block <= end_block) { + for (page = page_start; page < nb_pages; page++) { + if ((start_offset != 0U) || (length < dev_info.page_size)) { + /* Partial page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = MIN((size_t)(dev_info.page_size - start_offset), + length); + + memcpy((uint8_t *)buffer, scratch_buff + start_offset, + bytes_read); + start_offset = 0U; + } else { + /* Full page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = dev_info.page_size; + memcpy((uint8_t *)buffer, scratch_buff, bytes_read); + } + + length -= bytes_read; + buffer += bytes_read; + *out_length += bytes_read; + + /* All the bytes have read */ + if (length == 0U) { + break; + } + + udelay(CNF_READ_INT_DELAY_US); + } /* for */ + + page_start = 0U; + block++; + } /* while */ + + return 0; +} diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h new file mode 100644 index 000000000..f5dabdafa --- /dev/null +++ b/include/drivers/cadence/cdns_combo_phy.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_COMBOPHY_H +#define CDN_COMBOPHY_H + +/* SRS */ +#define SDMMC_CDN_SRS02 0x8 +#define SDMMC_CDN_SRS03 0xC +#define SDMMC_CDN_SRS04 0x10 +#define SDMMC_CDN_SRS05 0x14 +#define SDMMC_CDN_SRS06 0x18 +#define SDMMC_CDN_SRS07 0x1C +#define SDMMC_CDN_SRS09 0x24 +#define SDMMC_CDN_SRS10 0x28 +#define SDMMC_CDN_SRS11 0x2C +#define SDMMC_CDN_SRS12 0x30 +#define SDMMC_CDN_SRS13 0x34 +#define SDMMC_CDN_SRS14 0x38 + +/* SRS03 */ +/* Response Type Select + * Defines the expected response length. + */ +#define SDMMC_CDN_RTS 16 + +/* Command CRC Check Enable + * When set to 1, the host checks if the CRC field of the response is valid. + * When 0, the CRC check is disabled and the CRC field of the response is ignored. + */ +#define SDMMC_CDN_CRCCE 19 + +/* Command Index + * This field contains a command number (index) of the command to be sent. + */ +#define SDMMC_CDN_CIDX 24 + +/* SRS09 */ +/* Card Inserted + * Indicates if the card is inserted inside the slot. + */ +#define SDMMC_CDN_CI 16 + +/* SRS10 */ +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4. + */ +#define SDMMC_CDN_DTW 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode. + */ +#define SDMMC_CDN_EDTW 5 + +/* SD Bus Power for VDD1 + * When set to 1, the VDD1 voltage is supplied to card/device. + */ +#define SDMMC_CDN_BP 8 + +/* SD Bus Voltage Select + * This field is used to configure VDD1 voltage level. + */ +#define SDMMC_CDN_BVS 9 + +/* SRS11 */ +/* Internal Clock Enable + * This field is designated to controls (enable/disable) external clock generator. + */ +#define SDMMC_CDN_ICE 0 + +/* Internal Clock Stable + * When 1, indicates that the clock on sdmclk pin of the host is stable. + * When 0, indicates that the clock is not stable . + */ +#define SDMMC_CDN_ICS 1 + +/* SD Clock Enable + * When set, SDCLK clock is enabled. + * When clear, SDCLK clock is stopped. + */ +#define SDMMC_CDN_SDCE 2 + +/* USDCLK Frequency Select + * This is used to calculate frequency of USDCLK clock. + */ +#define SDMMC_CDN_USDCLKFS 6 + +/* SDCLK Frequency Select + * This is used to calculate frequency of SDCLK clock. + */ +#define SDMMC_CDN_SDCLKFS 8 + +/* Data Timeout Counter Value + * This value determines the interval by which DAT line timeouts are detected + */ +#define SDMMC_CDN_DTCV 16 + +/* SRS12 */ +/* Command Complete + * Generated when the end bit of the response is received. + */ +#define SDMMC_CDN_CC 0 + +/* Transfer Complete + * Generated when the transfer which uses the DAT line is complete. + */ +#define SDMMC_CDN_TC 1 + +/* Error Interrupt + * The software can check for an error by reading this single bit first. + */ +#define SDMMC_CDN_EINT 15 + +/* SRS14 */ +/* Command Complete Interrupt Enable */ +#define SDMMC_CDN_CC_IE 0 + +/* Transfer Complete Interrupt Enable */ +#define SDMMC_CDN_TC_IE 1 + +/* DMA Interrupt Enable */ +#define SDMMC_CDN_DMAINT_IE 3 + +/* Combo PHY DLL registers */ +#define CP_DLL_REG_BASE (0x10B92000) +#define CP_DLL_DQ_TIMING_REG (0x00) +#define CP_DLL_DQS_TIMING_REG (0x04) +#define CP_DLL_GATE_LPBK_CTRL_REG (0x08) +#define CP_DLL_MASTER_CTRL_REG (0x0C) +#define CP_DLL_SLAVE_CTRL_REG (0x10) +#define CP_DLL_IE_TIMING_REG (0x14) + +#define CP_DQ_TIMING_REG_SDR (0x00000002) +#define CP_DQS_TIMING_REG_SDR (0x00100004) +#define CP_GATE_LPBK_CTRL_REG_SDR (0x00D80000) +#define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000) +#define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000) + +#define CP_DLL(_reg) (CP_DLL_REG_BASE \ + + (CP_DLL_##_reg)) + +/* Control Timing Block registers */ +#define CP_CTB_REG_BASE (0x10B92080) +#define CP_CTB_CTRL_REG (0x00) +#define CP_CTB_TSEL_REG (0x04) +#define CP_CTB_GPIO_CTRL0 (0x08) +#define CP_CTB_GPIO_CTRL1 (0x0C) +#define CP_CTB_GPIO_STATUS0 (0x10) +#define CP_CTB_GPIO_STATUS1 (0x14) + +#define CP_CTRL_REG_SDR (0x00004040) +#define CP_TSEL_REG_SDR (0x00000000) + +#define CP_CTB(_reg) (CP_CTB_REG_BASE \ + + (CP_CTB_##_reg)) + +/* Combo PHY */ +#define SDMMC_CDN_REG_BASE 0x10808200 +#define PHY_DQ_TIMING_REG 0x2000 +#define PHY_DQS_TIMING_REG 0x2004 +#define PHY_GATE_LPBK_CTRL_REG 0x2008 +#define PHY_DLL_MASTER_CTRL_REG 0x200C +#define PHY_DLL_SLAVE_CTRL_REG 0x2010 +#define PHY_CTRL_REG 0x2080 +#define PHY_REG_ADDR_MASK 0xFFFF +#define PHY_REG_DATA_MASK 0xFFFFFFFF + +/* PHY_DQS_TIMING_REG */ +#define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 +#define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 +#define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 +#define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 + +/* PHY_GATE_LPBK_CTRL_REG */ +#define CP_SYNC_METHOD(x) ((x) << 31) //0x1 +#define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 +#define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f +#define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 +#define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 + +/* PHY_DLL_MASTER_CTRL_REG */ +#define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 +#define CP_DLL_START_POINT(x) ((x) << 0) //0xff + +/* PHY_DLL_SLAVE_CTRL_REG */ +#define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff +#define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff +#define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff +#define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff + +/* PHY_DQ_TIMING_REG */ +#define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1 +#define CP_IO_MASK_END(x) ((x) << 27) //0x7 +#define CP_IO_MASK_START(x) ((x) << 24) //0x7 +#define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7 + +/* PHY_CTRL_REG */ +#define CP_PHONY_DQS_TIMING_MASK 0x3F +#define CP_PHONY_DQS_TIMING_SHIFT 4 + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +struct cdns_sdmmc_combo_phy { + uint32_t cp_clk_wr_delay; + uint32_t cp_clk_wrdqs_delay; + uint32_t cp_data_select_oe_end; + uint32_t cp_dll_bypass_mode; + uint32_t cp_dll_locked_mode; + uint32_t cp_dll_start_point; + uint32_t cp_gate_cfg_always_on; + uint32_t cp_io_mask_always_on; + uint32_t cp_io_mask_end; + uint32_t cp_io_mask_start; + uint32_t cp_rd_del_sel; + uint32_t cp_read_dqs_cmd_delay; + uint32_t cp_read_dqs_delay; + uint32_t cp_sw_half_cycle_shift; + uint32_t cp_sync_method; + uint32_t cp_underrun_suppress; + uint32_t cp_use_ext_lpbk_dqs; + uint32_t cp_use_lpbk_dqs; + uint32_t cp_use_phony_dqs; + uint32_t cp_use_phony_dqs_cmd; +}; + +/* Function Prototype */ + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value); +int cdns_sd_card_detect(void); +int cdns_emmc_card_reset(void); + +#endif diff --git a/include/drivers/cadence/cdns_nand.h b/include/drivers/cadence/cdns_nand.h new file mode 100644 index 000000000..64ba2676d --- /dev/null +++ b/include/drivers/cadence/cdns_nand.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_NAND_H +#define CDN_NAND_H + +#include + +/* NAND flash device information */ +typedef struct cnf_dev_info { + uint8_t type; + uint8_t nluns; + uint8_t sector_cnt; + uint16_t npages_per_block; + uint16_t sector_size; + uint16_t last_sector_size; + uint16_t page_size; + uint16_t spare_size; + uint32_t nblocks_per_lun; + uint32_t block_size; + unsigned long long total_size; +} cnf_dev_info_t; + +/* Shared Macros */ + +/* Default values */ +#define CNF_DEF_VOL_ID 0 +#define CNF_DEF_DEVICE 0 +#define CNF_DEF_TRD 0 +#define CNF_READ_SINGLE_PAGE 1 +#define CNF_DEF_DELAY_US 500 +#define CNF_READ_INT_DELAY_US 10 + +/* Work modes */ +#define CNF_WORK_MODE_CDMA 0 +#define CNF_WORK_MODE_PIO 1 + +/* Command types */ +#define CNF_CT_SET_FEATURE 0x0100 +#define CNF_CT_RESET_ASYNC 0x1100 +#define CNF_CT_RESET_SYNC 0x1101 +#define CNF_CT_RESET_LUN 0x1102 +#define CNF_CT_ERASE 0x1000 +#define CNF_CT_PAGE_PROGRAM 0x2100 +#define CNF_CT_PAGE_READ 0x2200 + +/* Interrupts enable or disable */ +#define CNF_INT_EN 1 +#define CNF_INT_DIS 0 + +/* Device types */ +#define CNF_DT_UNKNOWN 0x00 +#define CNF_DT_ONFI 0x01 +#define CNF_DT_JEDEC 0x02 +#define CNF_DT_LEGACY 0x03 + +/* Command and status registers */ +#define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE + +/* DMA maximum burst size 0-127*/ +#define CNF_DMA_BURST_SIZE_MAX 127 + +/* DMA settings register field offsets */ +#define CNF_DMA_SETTINGS_BURST 0 +#define CNF_DMA_SETTINGS_OTE 16 +#define CNF_DMA_SETTINGS_SDMA_ERR 17 + +#define CNF_DMA_MASTER_SEL 1 +#define CNF_DMA_SLAVE_SEL 0 + +/* DMA FIFO trigger level register field offsets */ +#define CNF_FIFO_TLEVEL_POS 0 +#define CNF_FIFO_TLEVEL_DMA_SIZE 16 +#define CNF_DMA_PREFETCH_SIZE (1024 / 8) + +#define CNF_GET_CTRL_BUSY(x) (x & (1 << 8)) +#define CNF_GET_INIT_COMP(x) (x & (1 << 9)) + +/* Command register0 field offsets */ +#define CNF_CMDREG0_CT 30 +#define CNF_CMDREG0_TRD 24 +#define CNF_CMDREG0_INTR 20 +#define CNF_CMDREG0_DMA 21 +#define CNF_CMDREG0_VOL 16 +#define CNF_CMDREG0_CMD 0 +#define CNF_CMDREG4_MEM 24 + +/* Command status register field offsets */ +#define CNF_ECMD BIT(0) +#define CNF_EECC BIT(1) +#define CNF_EMAX BIT(2) +#define CNF_EDEV BIT(12) +#define CNF_EDQS BIT(13) +#define CNF_EFAIL BIT(14) +#define CNF_CMPLT BIT(15) +#define CNF_EBUS BIT(16) +#define CNF_EDI BIT(17) +#define CNF_EPAR BIT(18) +#define CNF_ECTX BIT(19) +#define CNF_EPRO BIT(20) +#define CNF_EIDX BIT(24) + +#define CNF_CMDREG_CMD_REG0 0x00 +#define CNF_CMDREG_CMD_REG1 0x04 +#define CNF_CMDREG_CMD_REG2 0x08 +#define CNF_CMDREG_CMD_REG3 0x0C +#define CNF_CMDREG_CMD_STAT_PTR 0x10 +#define CNF_CMDREG_CMD_STAT 0x14 +#define CNF_CMDREG_CMD_REG4 0x20 +#define CNF_CMDREG_CTRL_STATUS 0x118 +#define CNF_CMDREG_TRD_STATUS 0x120 + +#define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ + + (CNF_CMDREG_##_reg)) + +/* Controller configuration registers */ +#define CNF_LSB16_MASK 0xFFFF +#define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK) + +#define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_CTRLCFG_REG_BASE 0x10B80400 +#define CNF_CTRLCFG_TRANS_CFG0 0x00 +#define CNF_CTRLCFG_TRANS_CFG1 0x04 +#define CNF_CTRLCFG_LONG_POLL 0x08 +#define CNF_CTRLCFG_SHORT_POLL 0x0C +#define CNF_CTRLCFG_DEV_STAT 0x10 +#define CNF_CTRLCFG_DEV_LAYOUT 0x24 +#define CNF_CTRLCFG_ECC_CFG0 0x28 +#define CNF_CTRLCFG_ECC_CFG1 0x2C +#define CNF_CTRLCFG_MULTIPLANE_CFG 0x34 +#define CNF_CTRLCFG_CACHE_CFG 0x38 +#define CNF_CTRLCFG_DMA_SETTINGS 0x3C +#define CNF_CTRLCFG_FIFO_TLEVEL 0x54 + +#define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ + + (CNF_CTRLCFG_##_reg)) + +/* Data integrity registers */ +#define CNF_DI_PAR_EN 0 +#define CNF_DI_CRC_EN 1 + +#define CNF_DI_REG_BASE 0x10B80700 +#define CNF_DI_CONTROL 0x00 +#define CNF_DI_INJECT0 0x04 +#define CNF_DI_INJECT1 0x08 +#define CNF_DI_ERR_REG_ADDR 0x0C +#define CNF_DI_INJECT2 0x10 + +#define CNF_DI(_reg) (CNF_DI_REG_BASE \ + + (CNF_DI_##_reg)) + +/* Controller parameter registers */ +#define CNF_NTHREADS_MASK 0x07 +#define CNF_GET_NLUNS(x) (x & 0xFF) +#define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03) +#define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK)) + +#define CNF_CTRLPARAM_REG_BASE 0x10B80800 +#define CNF_CTRLPARAM_VERSION 0x00 +#define CNF_CTRLPARAM_FEATURE 0x04 +#define CNF_CTRLPARAM_MFR_ID 0x08 +#define CNF_CTRLPARAM_DEV_AREA 0x0C +#define CNF_CTRLPARAM_DEV_PARAMS0 0x10 +#define CNF_CTRLPARAM_DEV_PARAMS1 0x14 +#define CNF_CTRLPARAM_DEV_FEATUERS 0x18 +#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C + +#define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ + + (CNF_CTRLPARAM_##_reg)) + +/* Protection mechanism registers */ +#define CNF_PROT_REG_BASE 0x10B80900 +#define CNF_PROT_CTRL0 0x00 +#define CNF_PROT_DOWN0 0x04 +#define CNF_PROT_UP0 0x08 +#define CNF_PROT_CTRL1 0x10 +#define CNF_PROT_DOWN1 0x14 +#define CNF_PROT_UP1 0x18 + +#define CNF_PROT(_reg) (CNF_PROT_REG_BASE \ + + (CNF_PROT_##_reg)) + +/* Mini controller registers */ +#define CNF_MINICTRL_REG_BASE 0x10B81000 + +/* Operation work modes */ +#define CNF_OPR_WORK_MODE_SDR 0 +#define CNF_OPR_WORK_MODE_NVDDR 1 +#define CNF_OPR_WORK_MODE_TOGGLE_NVDDR2_3 2 +#define CNF_OPR_WORK_MODE_RES 3 + +/* Mini controller common settings register field offsets */ +#define CNF_CMN_SETTINGS_WR_WUP 20 +#define CNF_CMN_SETTINGS_RD_WUP 16 +#define CNF_CMN_SETTINGS_DEV16 8 +#define CNF_CMN_SETTINGS_OPR 0 + +/* Async mode register field offsets */ +#define CNF_ASYNC_TIMINGS_TRH 24 +#define CNF_ASYNC_TIMINGS_TRP 16 +#define CNF_ASYNC_TIMINGS_TWH 8 +#define CNF_ASYNC_TIMINGS_TWP 0 + +/* Mini controller DLL PHY controller register field offsets */ +#define CNF_DLL_PHY_RST_N 24 +#define CNF_DLL_PHY_EXT_WR_MODE 17 +#define CNF_DLL_PHY_EXT_RD_MODE 16 + +#define CNF_MINICTRL_WP_SETTINGS 0x00 +#define CNF_MINICTRL_RBN_SETTINGS 0x04 +#define CNF_MINICTRL_CMN_SETTINGS 0x08 +#define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C +#define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10 +#define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14 +#define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18 +#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C +#define CNF_MINICTRL_SYNC_TIMINGS 0x20 +#define CNF_MINICTRL_DLL_PHY_CTRL 0x34 + +#define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \ + + (CNF_MINICTRL_##_reg)) + +/* + * @brief Nand IO MTD initialization routine + * + * @total_size: [out] Total size of the NAND flash device + * @erase_size: [out] Minimum erase size of the NAND flash device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_init_mtd(unsigned long long *total_size, + unsigned int *erase_size); + +/* + * @brief Read bytes from the NAND flash device + * + * @offset: Byte offset to read from in device + * @buffer: [out] Bytes read from device + * @length: Number of bytes to read + * @out_length: [out] Number of bytes read from device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_read(unsigned int offset, uintptr_t buffer, + size_t length, size_t *out_length); + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void); + +#endif diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h new file mode 100644 index 000000000..645272535 --- /dev/null +++ b/include/drivers/cadence/cdns_sdmmc.h @@ -0,0 +1,474 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_MMC_H +#define CDN_MMC_H + +#include +#include +#include "socfpga_plat_def.h" + +#if MMC_DEVICE_TYPE == 0 +#define CONFIG_DMA_ADDR_T_64BIT 0 +#endif + +#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE +#define COMBO_PHY_REG 0x0 +#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7 +#define SDHC_DLL_RESET_MASK 0x00000001 +/* HRS09 */ +#define SDHC_PHY_SW_RESET BIT(0) +#define SDHC_PHY_INIT_COMPLETE BIT(1) +#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2) +#define EXTENDED_WR_MODE 3 +#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3) +#define RDCMD_EN 15 +#define SDHC_RDCMD_EN(x) ((x) << 15) +#define SDHC_RDDATA_EN(x) ((x) << 16) + +/* CMD_DATA_OUTPUT */ +#define SDHC_CDNS_HRS16 0x40 + +/* This value determines the interval by which DAT line timeouts are detected */ +/* The interval can be computed as below: */ +/* • 1111b - Reserved */ +/* • 1110b - t_sdmclk*2(27+2) */ +/* • 1101b - t_sdmclk*2(26+2) */ +#define READ_CLK 0xa << 16 +#define WRITE_CLK 0xe << 16 +#define DTC_VAL 0xE + +/* SRS00 */ +/* System Address / Argument 2 / 32-bit block count + * This field is used as: + * • 32-bit Block Count register + * • SDMA system memory address + * • Auto CMD23 Argument + */ +#define SAAR (1) + +/* SRS01 */ +/* Transfer Block Size + * This field defines block size for block data transfers + */ +#define BLOCK_SIZE 0 + +/* SDMA Buffer Boundary + * System address boundary can be set for SDMA engine. + */ +#define SDMA_BUF 7 << 12 + +/* Block Count For Current Transfer + * To set the number of data blocks can be defined for next transfer + */ +#define BLK_COUNT_CT 16 + +/* SRS03 */ +#define CMD_START (U(1) << 31) +#define CMD_USE_HOLD_REG (1 << 29) +#define CMD_UPDATE_CLK_ONLY (1 << 21) +#define CMD_SEND_INIT (1 << 15) +#define CMD_STOP_ABORT_CMD (4 << 22) +#define CMD_RESUME_CMD (2 << 22) +#define CMD_SUSPEND_CMD (1 << 22) +#define DATA_PRESENT (1 << 21) +#define CMD_IDX_CHK_ENABLE (1 << 20) +#define CMD_WRITE (0 << 4) +#define CMD_READ (1 << 4) +#define MULTI_BLK_READ (1 << 5) +#define RESP_ERR (1 << 7) +#define CMD_CHECK_RESP_CRC (1 << 19) +#define RES_TYPE_SEL_48 (2 << 16) +#define RES_TYPE_SEL_136 (1 << 16) +#define RES_TYPE_SEL_48_B (3 << 16) +#define RES_TYPE_SEL_NO (0 << 16) +#define DMA_ENABLED (1 << 0) +#define BLK_CNT_EN (1 << 1) +#define AUTO_CMD_EN (2 << 2) +#define COM_IDX 24 +#define ERROR_INT (1 << 15) +#define INT_SBE (1 << 13) +#define INT_HLE (1 << 12) +#define INT_FRUN (1 << 11) +#define INT_DRT (1 << 9) +#define INT_RTO (1 << 8) +#define INT_DCRC (1 << 7) +#define INT_RCRC (1 << 6) +#define INT_RXDR (1 << 5) +#define INT_TXDR (1 << 4) +#define INT_DTO (1 << 3) +#define INT_CMD_DONE (1 << 0) +#define TRAN_COMP (1 << 1) + +/* SRS09 */ +#define STATUS_DATA_BUSY BIT(2) + +/* SRS10 */ +/* LED Control + * State of this bit directly drives led port of the host + * in order to control the external LED diode + * Default value 0 << 1 + */ +#define LEDC BIT(0) +#define LEDC_OFF 0 << 1 + +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4 + * Default value 1 << 1 + */ +#define DT_WIDTH BIT(1) +#define DTW_4BIT 1 << 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode + * Default value 1 << 5 + */ +#define EDTW_8BIT 1 << 5 + +/* High Speed Enable + * Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1) + */ +#define HS_EN BIT(2) + +/* here 0 defines the 64 Kb size */ +#define MAX_64KB_PAGE 0 +#define EMMC_DESC_SIZE (1<<20) + +/* SRS11 */ +/* Software Reset For All + * When set to 1, the entire slot is reset + * After completing the reset operation, SRFA bit is automatically cleared + */ +#define SRFA BIT(24) + +/* Software Reset For CMD Line + * When set to 1, resets the logic related to the command generation and response checking + */ +#define SRCMD BIT(25) + +/* Software Reset For DAT Line + * When set to 1, resets the logic related to the data path, + * including data buffers and the DMA logic + */ +#define SRDAT BIT(26) + +/* SRS15 */ +/* UHS Mode Select + * Used to select one of UHS-I modes. + * • 000b - SDR12 + * • 001b - SDR25 + * • 010b - SDR50 + * • 011b - SDR104 + * • 100b - DDR50 + */ +#define SDR12_MODE 0 << 16 +#define SDR25_MODE 1 << 16 +#define SDR50_MODE 2 << 16 +#define SDR104_MODE 3 << 16 +#define DDR50_MODE 4 << 16 +/* 1.8V Signaling Enable + * • 0 - for Default Speed, High Speed mode + * • 1 - for UHS-I mode + */ +#define V18SE BIT(19) + +/* CMD23 Enable + * In result of Card Identification process, + * Host Driver set this bit to 1 if Card supports CMD23 + */ +#define CMD23_EN BIT(27) + +/* Host Version 4.00 Enable + * • 0 - Version 3.00 + * • 1 - Version 4.00 + */ +#define HV4E BIT(28) +/* Conf depends on SRS15.HV4E */ +#define SDMA 0 << 3 +#define ADMA2_32 2 << 3 +#define ADMA2_64 3 << 3 + +/* Preset Value Enable + * Setting this bit to 1 triggers an automatically update of SRS11 + */ +#define PVE BIT(31) + +#define BIT_AD_32 0 << 29 +#define BIT_AD_64 1 << 29 + +/* SW RESET REG*/ +#define SDHC_CDNS_HRS00 (0x00) +#define SDHC_CDNS_HRS00_SWR BIT(0) + +/* PHY access port */ +#define SDHC_CDNS_HRS04 0x10 +#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0) + +/* PHY data access port */ +#define SDHC_CDNS_HRS05 0x14 + +/* eMMC control registers */ +#define SDHC_CDNS_HRS06 0x18 + +/* SRS */ +#define SDHC_CDNS_SRS_BASE 0x200 +#define SDHC_CDNS_SRS00 0x200 +#define SDHC_CDNS_SRS01 0x204 +#define SDHC_CDNS_SRS02 0x208 +#define SDHC_CDNS_SRS03 0x20c +#define SDHC_CDNS_SRS04 0x210 +#define SDHC_CDNS_SRS05 0x214 +#define SDHC_CDNS_SRS06 0x218 +#define SDHC_CDNS_SRS07 0x21C +#define SDHC_CDNS_SRS08 0x220 +#define SDHC_CDNS_SRS09 0x224 +#define SDHC_CDNS_SRS09_CI BIT(16) +#define SDHC_CDNS_SRS10 0x228 +#define SDHC_CDNS_SRS11 0x22C +#define SDHC_CDNS_SRS12 0x230 +#define SDHC_CDNS_SRS13 0x234 +#define SDHC_CDNS_SRS14 0x238 +#define SDHC_CDNS_SRS15 0x23c +#define SDHC_CDNS_SRS21 0x254 +#define SDHC_CDNS_SRS22 0x258 +#define SDHC_CDNS_SRS23 0x25c + +/* HRS07 */ +#define SDHC_CDNS_HRS07 0x1c +#define SDHC_IDELAY_VAL(x) ((x) << 0) +#define SDHC_RW_COMPENSATE(x) ((x) << 16) + +/* PHY reset port */ +#define SDHC_CDNS_HRS09 0x24 + +/* HRS10 */ +/* PHY reset port */ +#define SDHC_CDNS_HRS10 0x28 + +/* HCSDCLKADJ DATA; DDR Mode */ +#define SDHC_HCSDCLKADJ(x) ((x) << 16) + +/* Pinmux headers will reomove after ATF driver implementation */ +#define PINMUX_SDMMC_SEL 0x0 +#define PIN0SEL 0x00 +#define PIN1SEL 0x04 +#define PIN2SEL 0x08 +#define PIN3SEL 0x0C +#define PIN4SEL 0x10 +#define PIN5SEL 0x14 +#define PIN6SEL 0x18 +#define PIN7SEL 0x1C +#define PIN8SEL 0x20 +#define PIN9SEL 0x24 +#define PIN10SEL 0x28 + +/* HRS16 */ +#define SDHC_WRCMD0_DLY(x) ((x) << 0) +#define SDHC_WRCMD1_DLY(x) ((x) << 4) +#define SDHC_WRDATA0_DLY(x) ((x) << 8) +#define SDHC_WRDATA1_DLY(x) ((x) << 12) +#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16) +#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20) +#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24) +#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28) + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +/* Refer to atf/tools/cert_create/include/debug.h */ +#define BIT_32(nr) (U(1) << (nr)) + +/* MMC Peripheral Definition */ +#define SOCFPGA_MMC_BLOCK_SIZE U(8192) +#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1)) +#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000) +#define MMC_RESPONSE_NONE 0 +#define SDHC_CDNS_SRS03_VALUE 0x01020013 + +/* Value randomly chosen for eMMC RCA, it should be > 1 */ +#define MMC_FIX_RCA 6 +#define RCA_SHIFT_OFFSET 16 + +#define CMD_EXTCSD_PARTITION_CONFIG 179 +#define CMD_EXTCSD_BUS_WIDTH 183 +#define CMD_EXTCSD_HS_TIMING 185 +#define CMD_EXTCSD_SEC_CNT 212 + +#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) +#define PART_CFG_PARTITION1_ACCESS (U(1) << 0) + +/* Values in EXT CSD register */ +#define MMC_BUS_WIDTH_1 U(0) +#define MMC_BUS_WIDTH_4 U(1) +#define MMC_BUS_WIDTH_8 U(2) +#define MMC_BUS_WIDTH_DDR_4 U(5) +#define MMC_BUS_WIDTH_DDR_8 U(6) +#define MMC_BOOT_MODE_BACKWARD (U(0) << 3) +#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) +#define MMC_BOOT_MODE_DDR (U(2) << 3) + +#define EXTCSD_SET_CMD (U(0) << 24) +#define EXTCSD_SET_BITS (U(1) << 24) +#define EXTCSD_CLR_BITS (U(2) << 24) +#define EXTCSD_WRITE_BYTES (U(3) << 24) +#define EXTCSD_CMD(x) (((x) & 0xff) << 16) +#define EXTCSD_VALUE(x) (((x) & 0xff) << 8) +#define EXTCSD_CMD_SET_NORMAL U(1) + +#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) +#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) +#define CSD_TRAN_SPEED_MULT_SHIFT 3 + +#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) +#define STATUS_READY_FOR_DATA BIT(8) +#define STATUS_SWITCH_ERROR BIT(7) +#define MMC_GET_STATE(x) (((x) >> 9) & 0xf) +#define MMC_STATE_IDLE 0 +#define MMC_STATE_READY 1 +#define MMC_STATE_IDENT 2 +#define MMC_STATE_STBY 3 +#define MMC_STATE_TRAN 4 +#define MMC_STATE_DATA 5 +#define MMC_STATE_RCV 6 +#define MMC_STATE_PRG 7 +#define MMC_STATE_DIS 8 +#define MMC_STATE_BTST 9 +#define MMC_STATE_SLP 10 + +#define MMC_FLAG_CMD23 (U(1) << 0) + +#define CMD8_CHECK_PATTERN U(0xAA) +#define VHS_2_7_3_6_V BIT(8) + +/*ADMA table component*/ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 + +enum sd_opcode { + SD_GO_IDLE_STATE = 0, + SD_ALL_SEND_CID = 2, + SD_SEND_RELATIVE_ADDR = 3, + SDIO_SEND_OP_COND = 5, /* SDIO cards only */ + SD_SWITCH = 6, + SD_SELECT_CARD = 7, + SD_SEND_IF_COND = 8, + SD_SEND_CSD = 9, + SD_SEND_CID = 10, + SD_VOL_SWITCH = 11, + SD_STOP_TRANSMISSION = 12, + SD_SEND_STATUS = 13, + SD_GO_INACTIVE_STATE = 15, + SD_SET_BLOCK_SIZE = 16, + SD_READ_SINGLE_BLOCK = 17, + SD_READ_MULTIPLE_BLOCK = 18, + SD_SEND_TUNING_BLOCK = 19, + SD_SET_BLOCK_COUNT = 23, + SD_WRITE_SINGLE_BLOCK = 24, + SD_WRITE_MULTIPLE_BLOCK = 25, + SD_ERASE_BLOCK_START = 32, + SD_ERASE_BLOCK_END = 33, + SD_ERASE_BLOCK_OPERATION = 38, + SD_APP_CMD = 55, + SD_SPI_READ_OCR = 58, /* SPI mode only */ + SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ +}; + +enum sd_app_cmd { + SD_APP_SET_BUS_WIDTH = 6, + SD_APP_SEND_STATUS = 13, + SD_APP_SEND_NUM_WRITTEN_BLK = 22, + SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, + SD_APP_SEND_OP_COND = 41, + SD_APP_CLEAR_CARD_DETECT = 42, + SD_APP_SEND_SCR = 51, +}; + +struct cdns_sdmmc_sdhc { + uint32_t sdhc_extended_rd_mode; + uint32_t sdhc_extended_wr_mode; + uint32_t sdhc_hcsdclkadj; + uint32_t sdhc_idelay_val; + uint32_t sdhc_rdcmd_en; + uint32_t sdhc_rddata_en; + uint32_t sdhc_rw_compensate; + uint32_t sdhc_sdcfsh; + uint32_t sdhc_sdcfsl; + uint32_t sdhc_wrcmd0_dly; + uint32_t sdhc_wrcmd0_sdclk_dly; + uint32_t sdhc_wrcmd1_dly; + uint32_t sdhc_wrcmd1_sdclk_dly; + uint32_t sdhc_wrdata0_dly; + uint32_t sdhc_wrdata0_sdclk_dly; + uint32_t sdhc_wrdata1_dly; + uint32_t sdhc_wrdata1_sdclk_dly; +}; + +enum sdmmc_device_mode { + SD_DS_ID, /* Identification */ + SD_DS, /* Default speed */ + SD_HS, /* High speed */ + SD_UHS_SDR12, /* Ultra high speed SDR12 */ + SD_UHS_SDR25, /* Ultra high speed SDR25 */ + SD_UHS_SDR50, /* Ultra high speed SDR`50 */ + SD_UHS_SDR104, /* Ultra high speed SDR104 */ + SD_UHS_DDR50, /* Ultra high speed DDR50 */ + EMMC_SDR_BC, /* SDR backward compatible */ + EMMC_SDR, /* SDR */ + EMMC_DDR, /* DDR */ + EMMC_HS200, /* High speed 200Mhz in SDR */ + EMMC_HS400, /* High speed 200Mhz in DDR */ + EMMC_HS400es, /* High speed 200Mhz in SDR with enhanced strobe*/ +}; + +struct cdns_sdmmc_params { + uintptr_t reg_base; + uintptr_t reg_pinmux; + uintptr_t reg_phy; + uintptr_t desc_base; + size_t desc_size; + int clk_rate; + int bus_width; + unsigned int flags; + enum sdmmc_device_mode cdn_sdmmc_dev_mode; + enum mmc_device_type cdn_sdmmc_dev_type; + uint32_t combophy; +}; + +/* read and write API */ +size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size); +size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size); + +struct cdns_idmac_desc { + /*8 bit attribute*/ + uint8_t attr; + /*reserved bits in desc*/ + uint8_t reserved; + /*page length for the descriptor*/ + uint16_t len; + /*lower 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_lo; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + /*higher 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_hi; +} __aligned(8); +#else +} __packed; +#endif + + + +/* Function Prototype */ +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg); +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, +struct cdns_sdmmc_sdhc *sdhc_reg); +#endif diff --git a/plat/intel/soc/common/drivers/combophy/combophy.c b/plat/intel/soc/common/drivers/combophy/combophy.c new file mode 100644 index 000000000..6c53bc11c --- /dev/null +++ b/plat/intel/soc/common/drivers/combophy/combophy.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "combophy.h" +#include "sdmmc/sdmmc.h" + +/* Temp assigned handoff data, need to remove when SDM up and run. */ +void config_nand(handoff *hoff_ptr) +{ + /* This is hardcoded input value for Combo PHY and SD host controller. */ + hoff_ptr->peripheral_pwr_gate_array = 0x40; + +} + +/* DFI configuration */ +int dfi_select(handoff *hoff_ptr) +{ + uint32_t data = 0; + + /* Temp assigned handoff data, need to remove when SDM up and run. */ + handoff reverse_handoff_ptr; + + /* Temp assigned handoff data, need to remove when SDM up and run. */ + config_nand(&reverse_handoff_ptr); + + if (((reverse_handoff_ptr.peripheral_pwr_gate_array) & PERIPHERAL_SDMMC_MASK) == 0U) { + ERROR("SDMMC/NAND is not set properly\n"); + return -ENXIO; + } + + mmio_setbits_32(SOCFPGA_SYSMGR(DFI_INTF), + (((reverse_handoff_ptr.peripheral_pwr_gate_array) & + PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)); + data = mmio_read_32(SOCFPGA_SYSMGR(DFI_INTF)); + if ((data & DFI_INTF_MASK) != (((reverse_handoff_ptr.peripheral_pwr_gate_array) & + PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)) { + ERROR("DFI is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int combo_phy_init(handoff *hoff_ptr) +{ + /* SDMMC/NAND DFI selection based on system manager DFI register */ + int ret = dfi_select(hoff_ptr); + + if (ret != 0U) { + ERROR("DFI configuration failed\n"); + return ret; + } + + return 0; +} diff --git a/plat/intel/soc/common/drivers/combophy/combophy.h b/plat/intel/soc/common/drivers/combophy/combophy.h new file mode 100644 index 000000000..ca571f7b4 --- /dev/null +++ b/plat/intel/soc/common/drivers/combophy/combophy.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef COMBOPHY_H +#define COMBOPHY_H + +#include + +#include "socfpga_handoff.h" + +#define PERIPHERAL_SDMMC_MASK 0x60 +#define PERIPHERAL_SDMMC_OFFSET 6 +#define DFI_INTF_MASK 0x1 + +/* FUNCTION DEFINATION */ +/* + * @brief Nand controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int combo_phy_init(handoff *hoff_ptr); +int dfi_select(handoff *hoff_ptr); + +#endif diff --git a/plat/intel/soc/common/drivers/nand/nand.c b/plat/intel/soc/common/drivers/nand/nand.c new file mode 100644 index 000000000..c6acbe3b1 --- /dev/null +++ b/plat/intel/soc/common/drivers/nand/nand.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include "nand.h" + +#include "agilex5_pinmux.h" +#include "combophy/combophy.h" + +/* Pinmux configuration */ +static void nand_pinmux_config(void) +{ + mmio_write_32(SOCFPGA_PINMUX(PIN0SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN1SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN2SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN3SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN4SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN5SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN6SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN7SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN8SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN9SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN10SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN11SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN12SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN13SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN14SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN16SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN17SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN18SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN19SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN20SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN21SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN22SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN23SEL), SOCFPGA_PINMUX_SEL_NAND); +} + +int nand_init(handoff *hoff_ptr) +{ + /* NAND pin mux configuration */ + nand_pinmux_config(); + + return cdns_nand_host_init(); +} diff --git a/plat/intel/soc/common/drivers/nand/nand.h b/plat/intel/soc/common/drivers/nand/nand.h new file mode 100644 index 000000000..b060a728d --- /dev/null +++ b/plat/intel/soc/common/drivers/nand/nand.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDR_H +#define DDR_H + +#include +#include "socfpga_handoff.h" + +/* FUNCTION DEFINATION */ +/* + * @brief Nand controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int nand_init(handoff *hoff_ptr); + +#endif diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index cecf56088..da8a8bdeb 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c @@ -13,6 +13,7 @@ #include #include "cadence_qspi.h" +#include "socfpga_plat_def.h" #define LESS(a, b) (((a) < (b)) ? (a) : (b)) #define MORE(a, b) (((a) > (b)) ? (a) : (b)) diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h index cfef5858c..104ab5fd0 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h @@ -10,8 +10,6 @@ #define CAD_QSPI_MICRON_N25Q_SUPPORT 1 -#define CAD_QSPI_OFFSET 0xff8d2000 - #define CAD_INVALID -1 #define CAD_QSPI_ERROR -2 @@ -38,8 +36,6 @@ #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd -#define CAD_QSPIDATA_OFST 0xff900000 - #define CAD_QSPI_DELAY 0xc #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8) diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c new file mode 100644 index 000000000..8666f54c2 --- /dev/null +++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c @@ -0,0 +1,769 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "agilex5_pinmux.h" +#include "sdmmc.h" + +static const struct mmc_ops *ops; +static unsigned int mmc_ocr_value; +static struct mmc_csd_emmc mmc_csd; +static struct sd_switch_status sd_switch_func_status; +static unsigned char mmc_ext_csd[512] __aligned(16); +static unsigned int mmc_flags; +static struct mmc_device_info *mmc_dev_info; +static unsigned int rca; +static unsigned int scr[2]__aligned(16) = { 0 }; + +extern const struct mmc_ops cdns_sdmmc_ops; +extern struct cdns_sdmmc_params cdns_params; +extern struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg; +extern struct cdns_sdmmc_sdhc sdmmc_sdhc_reg; + +static bool is_cmd23_enabled(void) +{ + return ((mmc_flags & MMC_FLAG_CMD23) != 0U); +} + +static bool is_sd_cmd6_enabled(void) +{ + return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U); +} + +/* TODO: Will romove once ATF driver is developed */ +void sdmmc_pin_config(void) +{ + /* temp use base + addr. Official must change to common method */ + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x00, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x04, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x08, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x0C, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x10, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x14, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x18, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x1C, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x20, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x24, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x28, 0x0); +} + +static int sdmmc_send_cmd(unsigned int idx, unsigned int arg, + unsigned int r_type, unsigned int *r_data) +{ + struct mmc_cmd cmd; + int ret; + + zeromem(&cmd, sizeof(struct mmc_cmd)); + + cmd.cmd_idx = idx; + cmd.cmd_arg = arg; + cmd.resp_type = r_type; + + ret = ops->send_cmd(&cmd); + + if ((ret == 0) && (r_data != NULL)) { + int i; + + for (i = 0; i < 4; i++) { + *r_data = cmd.resp_data[i]; + r_data++; + } + } + + if (ret != 0) { + VERBOSE("Send command %u error: %d\n", idx, ret); + } + + return ret; +} + +static int sdmmc_device_state(void) +{ + int retries = DEFAULT_SDMMC_MAX_RETRIES; + unsigned int resp_data[4]; + + do { + int ret; + + if (retries == 0) { + ERROR("CMD13 failed after %d retries\n", + DEFAULT_SDMMC_MAX_RETRIES); + return -EIO; + } + + ret = sdmmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, &resp_data[0]); + if (ret != 0) { + retries--; + continue; + } + + if ((resp_data[0] & STATUS_SWITCH_ERROR) != 0U) { + return -EIO; + } + + retries--; + } while ((resp_data[0] & STATUS_READY_FOR_DATA) == 0U); + + return MMC_GET_STATE(resp_data[0]); +} + +static int sdmmc_set_ext_csd(unsigned int ext_cmd, unsigned int value) +{ + int ret; + + ret = sdmmc_send_cmd(MMC_CMD(6), + EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) | + EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL, + MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret == MMC_STATE_PRG); + + return 0; +} + +static int sdmmc_mmc_sd_switch(unsigned int bus_width) +{ + int ret; + int retries = DEFAULT_SDMMC_MAX_RETRIES; + unsigned int bus_width_arg = 0; + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (ret != 0) { + return ret; + } + + ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr)); + if (ret != 0) { + return ret; + } + + /* ACMD51: SEND_SCR */ + do { + ret = sdmmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL); + if ((ret != 0) && (retries == 0)) { + ERROR("ACMD51 failed after %d retries (ret=%d)\n", + DEFAULT_SDMMC_MAX_RETRIES, ret); + return ret; + } + + retries--; + } while (ret != 0); + + ret = ops->read(0, (uintptr_t)&scr, sizeof(scr)); + if (ret != 0) { + return ret; + } + + if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) && + (bus_width == MMC_BUS_WIDTH_4)) { + bus_width_arg = 2; + } + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (ret != 0) { + return ret; + } + + /* ACMD6: SET_BUS_WIDTH */ + ret = sdmmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret == MMC_STATE_PRG); + + return 0; +} + +static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width) +{ + int ret; + unsigned int width = bus_width; + + if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) { + if (width == MMC_BUS_WIDTH_8) { + WARN("Wrong bus config for SD-card, force to 4\n"); + width = MMC_BUS_WIDTH_4; + } + ret = sdmmc_mmc_sd_switch(width); + if (ret != 0) { + return ret; + } + } else if (mmc_csd.spec_vers == 4U) { + ret = sdmmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, + (unsigned int)width); + if (ret != 0) { + return ret; + } + } else { + VERBOSE("Wrong MMC type or spec version\n"); + } + + return ops->set_ios(clk, width); +} + +static int sdmmc_fill_device_info(void) +{ + unsigned long long c_size; + unsigned int speed_idx; + unsigned int nb_blocks; + unsigned int freq_unit; + int ret = 0; + struct mmc_csd_sd_v2 *csd_sd_v2; + + switch (mmc_dev_info->mmc_dev_type) { + case MMC_IS_EMMC: + mmc_dev_info->block_size = MMC_BLOCK_SIZE; + + ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd, + sizeof(mmc_ext_csd)); + if (ret != 0) { + return ret; + } + + /* MMC CMD8: SEND_EXT_CSD */ + ret = sdmmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + ret = ops->read(0, (uintptr_t)&mmc_ext_csd, + sizeof(mmc_ext_csd)); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret != MMC_STATE_TRAN); + + nb_blocks = (mmc_ext_csd[CMD_EXTCSD_SEC_CNT] << 0) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 1] << 8) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24); + + mmc_dev_info->device_size = (unsigned long long)nb_blocks * + mmc_dev_info->block_size; + + break; + + case MMC_IS_SD: + /* + * Use the same mmc_csd struct, as required fields here + * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC. + */ + mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len); + + c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) | + (unsigned long long)mmc_csd.c_size_low; + assert(c_size != 0xFFFU); + + mmc_dev_info->device_size = (c_size + 1U) * + BIT_64(mmc_csd.c_size_mult + 2U) * + mmc_dev_info->block_size; + + break; + + case MMC_IS_SD_HC: + assert(mmc_csd.csd_structure == 1U); + + mmc_dev_info->block_size = MMC_BLOCK_SIZE; + + /* Need to use mmc_csd_sd_v2 struct */ + csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd; + c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) | + (unsigned long long)csd_sd_v2->c_size_low; + + mmc_dev_info->device_size = (c_size + 1U) << SDMMC_MULT_BY_512K_SHIFT; + + break; + + default: + ret = -EINVAL; + break; + } + + if (ret < 0) { + return ret; + } + + speed_idx = (mmc_csd.tran_speed & CSD_TRAN_SPEED_MULT_MASK) >> + CSD_TRAN_SPEED_MULT_SHIFT; + + assert(speed_idx > 0U); + + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx]; + } else { + mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx]; + } + + freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK; + while (freq_unit != 0U) { + mmc_dev_info->max_bus_freq *= 10U; + --freq_unit; + } + + mmc_dev_info->max_bus_freq *= 10000U; + + return 0; +} + +static int sdmmc_sd_switch(unsigned int mode, unsigned char group, + unsigned char func) +{ + unsigned int group_shift = (group - 1U) * 4U; + unsigned int group_mask = GENMASK(group_shift + 3U, group_shift); + unsigned int arg; + int ret; + + ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); + if (ret != 0) { + return ret; + } + + /* MMC CMD6: SWITCH_FUNC */ + arg = mode | SD_SWITCH_ALL_GROUPS_MASK; + arg &= ~group_mask; + arg |= func << group_shift; + ret = sdmmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + return ops->read(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); +} + +static int sdmmc_sd_send_op_cond(void) +{ + int n; + unsigned int resp_data[4]; + + for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) { + int ret; + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + /* ACMD41: SD_SEND_OP_COND */ + ret = sdmmc_send_cmd(MMC_ACMD(41), OCR_HCS | + mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3, + &resp_data[0]); + if (ret != 0) { + return ret; + } + + if ((resp_data[0] & OCR_POWERUP) != 0U) { + mmc_ocr_value = resp_data[0]; + + if ((mmc_ocr_value & OCR_HCS) != 0U) { + mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC; + } else { + mmc_dev_info->mmc_dev_type = MMC_IS_SD; + } + + return 0; + } + + mdelay(10); + } + + ERROR("ACMD41 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES); + + return -EIO; +} + +static int sdmmc_reset_to_idle(void) +{ + int ret; + + /* CMD0: reset to IDLE */ + ret = sdmmc_send_cmd(MMC_CMD(0), 0, 0, NULL); + if (ret != 0) { + return ret; + } + + mdelay(2); + + return 0; +} + +static int sdmmc_send_op_cond(void) +{ + int ret, n; + unsigned int resp_data[4]; + + ret = sdmmc_reset_to_idle(); + if (ret != 0) { + return ret; + } + + for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) { + ret = sdmmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE | + OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7, + MMC_RESPONSE_R3, &resp_data[0]); + if (ret != 0) { + return ret; + } + + if ((resp_data[0] & OCR_POWERUP) != 0U) { + mmc_ocr_value = resp_data[0]; + return 0; + } + + mdelay(10); + } + + ERROR("CMD1 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES); + + return -EIO; +} + +static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width) +{ + int ret; + unsigned int resp_data[4]; + + ops->init(); + + ret = sdmmc_reset_to_idle(); + if (ret != 0) { + return ret; + } + + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + ret = sdmmc_send_op_cond(); + } else { + /* CMD8: Send Interface Condition Command */ + ret = sdmmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN, + MMC_RESPONSE_R5, &resp_data[0]); + + if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) { + ret = sdmmc_sd_send_op_cond(); + } + } + if (ret != 0) { + return ret; + } + + /* CMD2: Card Identification */ + ret = sdmmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL); + if (ret != 0) { + return ret; + } + + /* CMD3: Set Relative Address */ + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + rca = MMC_FIX_RCA; + ret = sdmmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + } else { + ret = sdmmc_send_cmd(MMC_CMD(3), 0, + MMC_RESPONSE_R6, &resp_data[0]); + if (ret != 0) { + return ret; + } + + rca = (resp_data[0] & 0xFFFF0000U) >> 16; + } + + /* CMD9: CSD Register */ + ret = sdmmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R2, &resp_data[0]); + if (ret != 0) { + return ret; + } + + memcpy(&mmc_csd, &resp_data, sizeof(resp_data)); + + /* CMD7: Select Card */ + ret = sdmmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret != MMC_STATE_TRAN); + + ret = sdmmc_set_ios(clk, bus_width); + if (ret != 0) { + return ret; + } + + ret = sdmmc_fill_device_info(); + if (ret != 0) { + return ret; + } + + if (is_sd_cmd6_enabled() && + (mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) { + /* Try to switch to High Speed Mode */ + ret = sdmmc_sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) { + /* High speed not supported, keep default speed */ + return 0; + } + + ret = sdmmc_sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) { + /* Cannot switch to high speed, keep default speed */ + return 0; + } + + mmc_dev_info->max_bus_freq = 50000000U; + ret = ops->set_ios(clk, bus_width); + } + + return ret; +} + +size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size) +{ + int ret; + unsigned int cmd_idx, cmd_arg; + + assert((ops != NULL) && + (ops->read != NULL) && + (size != 0U) && + ((size & MMC_BLOCK_MASK) == 0U)); + + ret = ops->prepare(lba, buf, size); + if (ret != 0) { + return 0; + } + + if (is_cmd23_enabled()) { + /* Set block count */ + ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + cmd_idx = MMC_CMD(18); + } else { + if (size > MMC_BLOCK_SIZE) { + cmd_idx = MMC_CMD(18); + } else { + cmd_idx = MMC_CMD(17); + } + } + + if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) && + (mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) { + cmd_arg = lba * MMC_BLOCK_SIZE; + } else { + cmd_arg = lba; + } + + ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + ret = ops->read(lba, buf, size); + if (ret != 0) { + return 0; + } + + /* Wait buffer empty */ + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return 0; + } + } while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA)); + + if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) { + ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return 0; + } + } + + return size; +} + +size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size) +{ + int ret; + unsigned int cmd_idx, cmd_arg; + + assert((ops != NULL) && + (ops->write != NULL) && + (size != 0U) && + ((buf & MMC_BLOCK_MASK) == 0U) && + ((size & MMC_BLOCK_MASK) == 0U)); + + ret = ops->prepare(lba, buf, size); + if (ret != 0) { + return 0; + } + + if (is_cmd23_enabled()) { + /* Set block count */ + ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + cmd_idx = MMC_CMD(25); + } else { + if (size > MMC_BLOCK_SIZE) { + cmd_idx = MMC_CMD(25); + } else { + cmd_idx = MMC_CMD(24); + } + } + + if ((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) { + cmd_arg = lba * MMC_BLOCK_SIZE; + } else { + cmd_arg = lba; + } + + ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + ret = ops->write(lba, buf, size); + if (ret != 0) { + return 0; + } + + /* Wait buffer empty */ + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return 0; + } + } while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_RCV)); + + if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) { + ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return 0; + } + } + + return size; +} + +int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, + unsigned int width, unsigned int flags, + struct mmc_device_info *device_info) +{ + assert((ops_ptr != NULL) && + (ops_ptr->init != NULL) && + (ops_ptr->send_cmd != NULL) && + (ops_ptr->set_ios != NULL) && + (ops_ptr->prepare != NULL) && + (ops_ptr->read != NULL) && + (ops_ptr->write != NULL) && + (device_info != NULL) && + (clk != 0) && + ((width == MMC_BUS_WIDTH_1) || + (width == MMC_BUS_WIDTH_4) || + (width == MMC_BUS_WIDTH_8) || + (width == MMC_BUS_WIDTH_DDR_4) || + (width == MMC_BUS_WIDTH_DDR_8))); + + ops = ops_ptr; + mmc_flags = flags; + mmc_dev_info = device_info; + + return sdmmc_enumerate(clk, width); +} + +int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, struct mmc_device_info *info) +{ + int result = 0; + + /* SDMMC pin mux configuration */ + sdmmc_pin_config(); + cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (result < 0) { + return result; + } + + assert((params != NULL) && + ((params->reg_base & MMC_BLOCK_MASK) == 0) && + ((params->desc_base & MMC_BLOCK_MASK) == 0) && + ((params->desc_size & MMC_BLOCK_MASK) == 0) && + ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) && + ((params->reg_phy & MMC_BLOCK_MASK) == 0) && + (params->desc_size > 0) && + (params->clk_rate > 0) && + ((params->bus_width == MMC_BUS_WIDTH_1) || + (params->bus_width == MMC_BUS_WIDTH_4) || + (params->bus_width == MMC_BUS_WIDTH_8))); + + memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params)); + cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type; + cdns_params.cdn_sdmmc_dev_mode = SD_DS; + + result = sd_or_mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width, + params->flags, info); + + return result; +} diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h new file mode 100644 index 000000000..16c6b04b9 --- /dev/null +++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SDMMC_H +#define SDMMC_H + +#include +#include "socfpga_handoff.h" + +#define PERIPHERAL_SDMMC_MASK 0x60 +#define PERIPHERAL_SDMMC_OFFSET 6 + +#define DEFAULT_SDMMC_MAX_RETRIES 5 +#define SEND_SDMMC_OP_COND_MAX_RETRIES 100 +#define SDMMC_MULT_BY_512K_SHIFT 19 + +static const unsigned char tran_speed_base[16] = { + 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 +}; + +static const unsigned char sd_tran_speed_base[16] = { + 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 +}; + + +/* FUNCTION DEFINATION */ +/* + * @brief SDMMC controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, + struct mmc_device_info *info); +int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, + unsigned int width, unsigned int flags, + struct mmc_device_info *device_info); +void sdmmc_pin_config(void); +#endif diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c index ac7a9da86..e80f0747d 100644 --- a/plat/intel/soc/common/socfpga_storage.c +++ b/plat/intel/soc/common/socfpga_storage.c @@ -22,6 +22,7 @@ #include #include +#include "drivers/sdmmc/sdmmc.h" #include "socfpga_private.h" @@ -144,8 +145,8 @@ void socfpga_io_setup(int boot_source) register_io_dev = ®ister_io_dev_block; boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE; boot_dev_spec.buffer.length = SOCFPGA_MMC_BLOCK_SIZE; - boot_dev_spec.ops.read = mmc_read_blocks; - boot_dev_spec.ops.write = mmc_write_blocks; + boot_dev_spec.ops.read = SDMMC_READ_BLOCKS; + boot_dev_spec.ops.write = SDMMC_WRITE_BLOCKS; boot_dev_spec.block_size = MMC_BLOCK_SIZE; break;